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[RFC v3 45/71] target/riscv: rvv-1.0: narrowing integer right shift inst
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From: |
frank . chang |
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Subject: |
[RFC v3 45/71] target/riscv: rvv-1.0: narrowing integer right shift instructions |
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Date: |
Thu, 6 Aug 2020 18:46:42 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 24 ++++++++++----------
target/riscv/insn32.decode | 12 +++++-----
target/riscv/insn_trans/trans_rvv.inc.c | 30 ++++++++++++-------------
target/riscv/vector_helper.c | 24 ++++++++++----------
4 files changed, 45 insertions(+), 45 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 3560bf1d4f5..fe37bd2f4af 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -397,18 +397,18 @@ DEF_HELPER_6(vsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsra_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsra_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsra_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_wx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_wx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_wx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vmseq_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmseq_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e62bad906a3..c4fe9767585 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -370,12 +370,12 @@ vsrl_vi 101000 . ..... ..... 011 ..... 1010111
@r_vm
vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
-vnsrl_vv 101100 . ..... ..... 000 ..... 1010111 @r_vm
-vnsrl_vx 101100 . ..... ..... 100 ..... 1010111 @r_vm
-vnsrl_vi 101100 . ..... ..... 011 ..... 1010111 @r_vm
-vnsra_vv 101101 . ..... ..... 000 ..... 1010111 @r_vm
-vnsra_vx 101101 . ..... ..... 100 ..... 1010111 @r_vm
-vnsra_vi 101101 . ..... ..... 011 ..... 1010111 @r_vm
+vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm
+vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm
+vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm
+vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm
+vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm
+vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm
vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm
vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm
vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 2f5846fe4f0..196f1858465 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1906,7 +1906,7 @@ GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx,
shri)
GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari)
/* Vector Narrowing Integer Right Shift Instructions */
-static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
+static bool opiwv_narrow_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
vext_check_isa_ill(s) &&
@@ -1914,10 +1914,10 @@ static bool opivv_narrow_check(DisasContext *s,
arg_rmrr *a)
}
/* OPIVV with NARROW */
-#define GEN_OPIVV_NARROW_TRANS(NAME) \
+#define GEN_OPIWV_NARROW_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
- if (opivv_narrow_check(s, a)) { \
+ if (opiwv_narrow_check(s, a)) { \
uint32_t data = 0; \
static gen_helper_gvec_4_ptr * const fns[3] = { \
gen_helper_##NAME##_b, \
@@ -1939,10 +1939,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
} \
return false; \
}
-GEN_OPIVV_NARROW_TRANS(vnsra_vv)
-GEN_OPIVV_NARROW_TRANS(vnsrl_vv)
+GEN_OPIWV_NARROW_TRANS(vnsra_wv)
+GEN_OPIWV_NARROW_TRANS(vnsrl_wv)
-static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
+static bool opiwx_narrow_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
vext_check_isa_ill(s) &&
@@ -1950,10 +1950,10 @@ static bool opivx_narrow_check(DisasContext *s,
arg_rmrr *a)
}
/* OPIVX with NARROW */
-#define GEN_OPIVX_NARROW_TRANS(NAME) \
+#define GEN_OPIWX_NARROW_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
- if (opivx_narrow_check(s, a)) { \
+ if (opiwx_narrow_check(s, a)) { \
static gen_helper_opivx * const fns[3] = { \
gen_helper_##NAME##_b, \
gen_helper_##NAME##_h, \
@@ -1964,14 +1964,14 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
return false; \
}
-GEN_OPIVX_NARROW_TRANS(vnsra_vx)
-GEN_OPIVX_NARROW_TRANS(vnsrl_vx)
+GEN_OPIWX_NARROW_TRANS(vnsra_wx)
+GEN_OPIWX_NARROW_TRANS(vnsrl_wx)
-/* OPIVI with NARROW */
-#define GEN_OPIVI_NARROW_TRANS(NAME, IMM_MODE, OPIVX) \
+/* OPIWI with NARROW */
+#define GEN_OPIWI_NARROW_TRANS(NAME, IMM_MODE, OPIVX) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
- if (opivx_narrow_check(s, a)) { \
+ if (opiwx_narrow_check(s, a)) { \
static gen_helper_opivx * const fns[3] = { \
gen_helper_##OPIVX##_b, \
gen_helper_##OPIVX##_h, \
@@ -1983,8 +1983,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
return false; \
}
-GEN_OPIVI_NARROW_TRANS(vnsra_vi, IMM_ZX, vnsra_vx)
-GEN_OPIVI_NARROW_TRANS(vnsrl_vi, IMM_ZX, vnsrl_vx)
+GEN_OPIWI_NARROW_TRANS(vnsra_wi, IMM_ZX, vnsra_wx)
+GEN_OPIWI_NARROW_TRANS(vnsrl_wi, IMM_ZX, vnsrl_wx)
/* Vector Integer Comparison Instructions */
/*
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index cc501a7cb44..0bed365c8f0 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1395,18 +1395,18 @@ GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4,
DO_SRL, 0x1f)
GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f)
/* Vector Narrowing Integer Right Shift Instructions */
-GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf)
-GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f)
-GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f)
-GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf)
-GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f)
-GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f)
-GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf)
-GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f)
-GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f)
-GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf)
-GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f)
-GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f)
+GEN_VEXT_SHIFT_VV(vnsrl_wv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf)
+GEN_VEXT_SHIFT_VV(vnsrl_wv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f)
+GEN_VEXT_SHIFT_VV(vnsrl_wv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f)
+GEN_VEXT_SHIFT_VV(vnsra_wv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf)
+GEN_VEXT_SHIFT_VV(vnsra_wv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f)
+GEN_VEXT_SHIFT_VV(vnsra_wv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f)
+GEN_VEXT_SHIFT_VX(vnsrl_wx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf)
+GEN_VEXT_SHIFT_VX(vnsrl_wx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f)
+GEN_VEXT_SHIFT_VX(vnsrl_wx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f)
+GEN_VEXT_SHIFT_VX(vnsra_wx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf)
+GEN_VEXT_SHIFT_VX(vnsra_wx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f)
+GEN_VEXT_SHIFT_VX(vnsra_wx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f)
/* Vector Integer Comparison Instructions */
#define DO_MSEQ(N, M) (N == M)
--
2.17.1
- [RFC v3 35/71] target/riscv: rvv-1.0: allow load element with sign-extended, (continued)
- [RFC v3 35/71] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2020/08/06
- [RFC v3 36/71] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2020/08/06
- [RFC v3 38/71] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2020/08/06
- [RFC v3 39/71] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2020/08/06
- [RFC v3 37/71] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2020/08/06
- [RFC v3 40/71] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2020/08/06
- [RFC v3 41/71] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2020/08/06
- [RFC v3 42/71] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2020/08/06
- [RFC v3 43/71] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2020/08/06
- [RFC v3 44/71] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2020/08/06
- [RFC v3 45/71] target/riscv: rvv-1.0: narrowing integer right shift instructions,
frank . chang <=
- [RFC v3 46/71] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2020/08/06
- [RFC v3 47/71] target/riscv: rvv-1.0: add Zvqmac extension, frank . chang, 2020/08/06
- [RFC v3 48/71] target/riscv: rvv-1.0: quad-widening integer multiply-add instructions, frank . chang, 2020/08/06
- [RFC v3 49/71] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2020/08/06
- [RFC v3 51/71] target/riscv: use softfloat lib float16 comparison functions, frank . chang, 2020/08/06
- [RFC v3 50/71] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2020/08/06
- [RFC v3 52/71] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2020/08/06
- [RFC v3 53/71] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2020/08/06
- [RFC v3 54/71] target/riscv: rvv-1.0: slide instructions, frank . chang, 2020/08/06
- [RFC v3 55/71] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2020/08/06