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[RFC v3 53/71] target/riscv: rvv-1.0: mask-register logical instructions
From: |
frank . chang |
Subject: |
[RFC v3 53/71] target/riscv: rvv-1.0: mask-register logical instructions |
Date: |
Thu, 6 Aug 2020 18:46:50 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Clear tail elements only if VTA is agnostic.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 3 ++-
target/riscv/vector_helper.c | 4 ----
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 0a86d41b0a4..aab51a94bbf 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2975,7 +2975,8 @@ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
#define GEN_MM_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_r *a) \
{ \
- if (vext_check_isa_ill(s)) { \
+ if (require_rvv(s) && \
+ vext_check_isa_ill(s)) { \
uint32_t data = 0; \
gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
TCGLabel *over = gen_new_label(); \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index d8aa0825647..59c35343790 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4508,7 +4508,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vl = env->vl; \
uint32_t i; \
int a, b; \
@@ -4518,9 +4517,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
b = vext_elem_mask(vs2, i); \
vext_set_elem_mask(vd, i, OP(b, a)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
}
#define DO_NAND(N, M) (!(N & M))
--
2.17.1
- [RFC v3 43/71] target/riscv: rvv-1.0: single-width bit shift instructions, (continued)
- [RFC v3 43/71] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2020/08/06
- [RFC v3 44/71] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2020/08/06
- [RFC v3 45/71] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2020/08/06
- [RFC v3 46/71] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2020/08/06
- [RFC v3 47/71] target/riscv: rvv-1.0: add Zvqmac extension, frank . chang, 2020/08/06
- [RFC v3 48/71] target/riscv: rvv-1.0: quad-widening integer multiply-add instructions, frank . chang, 2020/08/06
- [RFC v3 49/71] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2020/08/06
- [RFC v3 51/71] target/riscv: use softfloat lib float16 comparison functions, frank . chang, 2020/08/06
- [RFC v3 50/71] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2020/08/06
- [RFC v3 52/71] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2020/08/06
- [RFC v3 53/71] target/riscv: rvv-1.0: mask-register logical instructions,
frank . chang <=
- [RFC v3 54/71] target/riscv: rvv-1.0: slide instructions, frank . chang, 2020/08/06
- [RFC v3 55/71] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2020/08/06
- [RFC v3 56/71] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2020/08/06
- [RFC v3 57/71] target/riscv: rvv-1.0: single-width floating-point reduction, frank . chang, 2020/08/06
- [RFC v3 58/71] target/riscv: rvv-1.0: widening floating-point reduction instructions, frank . chang, 2020/08/06
- [RFC v3 59/71] target/riscv: rvv-1.0: single-width scaling shift instructions, frank . chang, 2020/08/06
- [RFC v3 60/71] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2020/08/06
- [RFC v3 61/71] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 2020/08/06
- [RFC v3 62/71] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2020/08/06
- [RFC v3 63/71] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2020/08/06