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[PATCH v3 06/13] target/riscv: Fix the interrupt cause code
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From: |
Alistair Francis |
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Subject: |
[PATCH v3 06/13] target/riscv: Fix the interrupt cause code |
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Date: |
Wed, 12 Aug 2020 12:13:30 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b5f4264525..9ab3ca4675 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -909,14 +909,15 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
!force_hs_execp) {
+ /* Trap to VS mode */
/*
* See if we need to adjust cause. Yes if its VS mode interrupt
* no if hypervisor has delegated one of hs mode's interrupt
*/
if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
- cause == IRQ_VS_EXT)
+ cause == IRQ_VS_EXT) {
cause = cause - 1;
- /* Trap to VS mode */
+ }
env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
} else if (riscv_cpu_virt_enabled(env)) {
/* Trap into HS mode, from virt */
--
2.27.0
- [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1, Alistair Francis, 2020/08/12
- [PATCH v3 01/13] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/08/12
- [PATCH v3 02/13] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/12
- [PATCH v3 03/13] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/12
- [PATCH v3 04/13] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/08/12
- [PATCH v3 05/13] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/08/12
- [PATCH v3 06/13] target/riscv: Fix the interrupt cause code,
Alistair Francis <=
- [PATCH v3 07/13] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/08/12
- [PATCH v3 08/13] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/08/12
- [PATCH v3 09/13] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/08/12
- [PATCH v3 10/13] target/riscv: Only support little endian guests, Alistair Francis, 2020/08/12
- [PATCH v3 12/13] target/riscv: Return the exception from invalid CSR accesses, Alistair Francis, 2020/08/12
- [PATCH v3 11/13] target/riscv: Support the v0.6 Hypervisor extension CRSs, Alistair Francis, 2020/08/12
- [PATCH v3 13/13] target/riscv: Support the Virtual Instruction fault, Alistair Francis, 2020/08/12
- Re: [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1, LIU Zhiwei, 2020/08/12