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[PATCH v3 10/13] target/riscv: Only support little endian guests
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From: |
Alistair Francis |
|
Subject: |
[PATCH v3 10/13] target/riscv: Only support little endian guests |
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Date: |
Wed, 12 Aug 2020 12:13:41 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 390ef781e4..5e50683c58 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -840,6 +840,8 @@ static int read_hstatus(CPURISCVState *env, int csrno,
target_ulong *val)
/* We only support 64-bit VSXL */
*val = set_field(*val, HSTATUS_VSXL, 2);
#endif
+ /* We only support little endian */
+ *val = set_field(*val, HSTATUS_VSBE, 0);
return 0;
}
@@ -851,6 +853,9 @@ static int write_hstatus(CPURISCVState *env, int csrno,
target_ulong val)
qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN
options.");
}
#endif
+ if (get_field(val, HSTATUS_VSBE) != 0) {
+ qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
+ }
return 0;
}
--
2.27.0
- [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1, Alistair Francis, 2020/08/12
- [PATCH v3 01/13] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/08/12
- [PATCH v3 02/13] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/12
- [PATCH v3 03/13] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/12
- [PATCH v3 04/13] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/08/12
- [PATCH v3 05/13] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/08/12
- [PATCH v3 06/13] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/08/12
- [PATCH v3 07/13] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/08/12
- [PATCH v3 08/13] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/08/12
- [PATCH v3 09/13] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/08/12
- [PATCH v3 10/13] target/riscv: Only support little endian guests,
Alistair Francis <=
- [PATCH v3 12/13] target/riscv: Return the exception from invalid CSR accesses, Alistair Francis, 2020/08/12
- [PATCH v3 11/13] target/riscv: Support the v0.6 Hypervisor extension CRSs, Alistair Francis, 2020/08/12
- [PATCH v3 13/13] target/riscv: Support the Virtual Instruction fault, Alistair Francis, 2020/08/12
- Re: [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1, LIU Zhiwei, 2020/08/12