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[PATCH v3 08/13] target/riscv: Update the CSRs to the v0.6 Hyp extension
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From: |
Alistair Francis |
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Subject: |
[PATCH v3 08/13] target/riscv: Update the CSRs to the v0.6 Hyp extension |
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Date: |
Wed, 12 Aug 2020 12:13:36 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fb6a3e9092..573d85da41 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -437,15 +437,17 @@
#endif
/* hstatus CSR bits */
-#define HSTATUS_SPRV 0x00000001
+#define HSTATUS_VSBE 0x00000020
+#define HSTATUS_GVA 0x00000040
#define HSTATUS_SPV 0x00000080
-#define HSTATUS_SP2P 0x00000100
-#define HSTATUS_SP2V 0x00000200
+#define HSTATUS_SPVP 0x00000100
+#define HSTATUS_HU 0x00000200
+#define HSTATUS_VGEIN 0x0003F000
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTSR 0x00400000
-#define HSTATUS_HU 0x00000200
-#define HSTATUS_GVA 0x00000040
-#define HSTATUS_SPVP 0x00000100
+#if defined(TARGET_RISCV64)
+#define HSTATUS_VSXL 0x300000000
+#endif
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
--
2.27.0
- [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1, Alistair Francis, 2020/08/12
- [PATCH v3 01/13] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/08/12
- [PATCH v3 02/13] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/12
- [PATCH v3 03/13] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/12
- [PATCH v3 04/13] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/08/12
- [PATCH v3 05/13] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/08/12
- [PATCH v3 06/13] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/08/12
- [PATCH v3 07/13] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/08/12
- [PATCH v3 08/13] target/riscv: Update the CSRs to the v0.6 Hyp extension,
Alistair Francis <=
- [PATCH v3 09/13] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/08/12
- [PATCH v3 10/13] target/riscv: Only support little endian guests, Alistair Francis, 2020/08/12
- [PATCH v3 12/13] target/riscv: Return the exception from invalid CSR accesses, Alistair Francis, 2020/08/12
- [PATCH v3 11/13] target/riscv: Support the v0.6 Hypervisor extension CRSs, Alistair Francis, 2020/08/12
- [PATCH v3 13/13] target/riscv: Support the Virtual Instruction fault, Alistair Francis, 2020/08/12
- Re: [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1, LIU Zhiwei, 2020/08/12