[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v3 11/13] target/riscv: Support the v0.6 Hypervisor extension CRS
|
From: |
Alistair Francis |
|
Subject: |
[PATCH v3 11/13] target/riscv: Support the v0.6 Hypervisor extension CRSs |
|
Date: |
Wed, 12 Aug 2020 12:13:44 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 3 +++
target/riscv/csr.c | 40 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 573d85da41..d88e2ea30d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -197,9 +197,12 @@
#define CSR_HIDELEG 0x603
#define CSR_HIE 0x604
#define CSR_HCOUNTEREN 0x606
+#define CSR_HGEIE 0x607
#define CSR_HTVAL 0x643
+#define CSR_HVIP 0x645
#define CSR_HIP 0x644
#define CSR_HTINST 0x64A
+#define CSR_HGEIP 0xE12
#define CSR_HGATP 0x680
#define CSR_HTIMEDELTA 0x605
#define CSR_HTIMEDELTAH 0x615
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5e50683c58..7dc50e6299 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -883,12 +883,25 @@ static int write_hideleg(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
+static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+ target_ulong new_value, target_ulong write_mask)
+{
+ int ret = rmw_mip(env, 0, ret_value, new_value,
+ write_mask & hip_writable_mask);
+
+ *ret_value &= hip_writable_mask;
+
+ return ret;
+}
+
static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
int ret = rmw_mip(env, 0, ret_value, new_value,
write_mask & hip_writable_mask);
+ *ret_value &= hip_writable_mask;
+
return ret;
}
@@ -916,6 +929,18 @@ static int write_hcounteren(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
+static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ return 0;
+}
+
+static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
+{
+ qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ return 0;
+}
+
static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->htval;
@@ -939,6 +964,18 @@ static int write_htinst(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
+static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ return 0;
+}
+
+static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
+{
+ qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ return 0;
+}
+
static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->hgatp;
@@ -1341,11 +1378,14 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus
},
[CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg
},
[CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg
},
+ [CSR_HVIP] = { hmode, NULL, NULL, rmw_hvip
},
[CSR_HIP] = { hmode, NULL, NULL, rmw_hip
},
[CSR_HIE] = { hmode, read_hie, write_hie
},
[CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren
},
+ [CSR_HGEIE] = { hmode, read_hgeie, write_hgeie
},
[CSR_HTVAL] = { hmode, read_htval, write_htval
},
[CSR_HTINST] = { hmode, read_htinst, write_htinst
},
+ [CSR_HGEIP] = { hmode, read_hgeip, write_hgeip
},
[CSR_HGATP] = { hmode, read_hgatp, write_hgatp
},
[CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta
},
#if defined(TARGET_RISCV32)
--
2.27.0
- [PATCH v3 02/13] target/riscv: Allow generating hlv/hlvx/hsv instructions, (continued)
- [PATCH v3 02/13] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/12
- [PATCH v3 03/13] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/12
- [PATCH v3 04/13] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/08/12
- [PATCH v3 05/13] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/08/12
- [PATCH v3 06/13] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/08/12
- [PATCH v3 07/13] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/08/12
- [PATCH v3 08/13] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/08/12
- [PATCH v3 09/13] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/08/12
- [PATCH v3 10/13] target/riscv: Only support little endian guests, Alistair Francis, 2020/08/12
- [PATCH v3 12/13] target/riscv: Return the exception from invalid CSR accesses, Alistair Francis, 2020/08/12
- [PATCH v3 11/13] target/riscv: Support the v0.6 Hypervisor extension CRSs,
Alistair Francis <=
- [PATCH v3 13/13] target/riscv: Support the Virtual Instruction fault, Alistair Francis, 2020/08/12
- Re: [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1, LIU Zhiwei, 2020/08/12