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[PULL 23/61] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and
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From: |
Alistair Francis |
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Subject: |
[PULL 23/61] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns |
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Date: |
Fri, 21 Jan 2022 15:57:52 +1000 |
From: Frank Chang <frank.chang@sifive.com>
All Zve* extensions support all vector fixed-point arithmetic
instructions, except that vsmul.vv and vsmul.vx are not supported
for EEW=64 in Zve64*.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-6-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 27 +++++++++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index e64dddda28..8e493b7933 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2123,8 +2123,31 @@ GEN_OPIVX_TRANS(vasub_vx, opivx_check)
GEN_OPIVX_TRANS(vasubu_vx, opivx_check)
/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
-GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
-GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
+
+static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
+{
+ /*
+ * All Zve* extensions support all vector fixed-point arithmetic
+ * instructions, except that vsmul.vv and vsmul.vx are not supported
+ * for EEW=64 in Zve64*. (Section 18.2)
+ */
+ return opivv_check(s, a) &&
+ (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+}
+
+static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
+{
+ /*
+ * All Zve* extensions support all vector fixed-point arithmetic
+ * instructions, except that vsmul.vv and vsmul.vx are not supported
+ * for EEW=64 in Zve64*. (Section 18.2)
+ */
+ return opivx_check(s, a) &&
+ (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+}
+
+GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)
+GEN_OPIVX_TRANS(vsmul_vx, vsmul_vx_check)
/* Vector Single-Width Scaling Shift Instructions */
GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
--
2.31.1
- [PULL 12/61] target/riscv: Add host cpu type, (continued)
- [PULL 12/61] target/riscv: Add host cpu type, Alistair Francis, 2022/01/21
- [PULL 13/61] target/riscv: Add kvm_riscv_get/put_regs_timer, Alistair Francis, 2022/01/21
- [PULL 08/61] target/riscv: Implement kvm_arch_put_registers, Alistair Francis, 2022/01/21
- [PULL 14/61] target/riscv: Implement virtual time adjusting with vm state changing, Alistair Francis, 2022/01/21
- [PULL 15/61] target/riscv: Support virtual time context synchronization, Alistair Francis, 2022/01/21
- [PULL 16/61] target/riscv: enable riscv kvm accel, Alistair Francis, 2022/01/21
- [PULL 17/61] softmmu/device_tree: Silence compiler warning with --enable-sanitizers, Alistair Francis, 2022/01/21
- [PULL 18/61] softmmu/device_tree: Remove redundant pointer assignment, Alistair Francis, 2022/01/21
- [PULL 21/61] target/riscv: rvv-1.0: Add Zve64f support for load and store insns, Alistair Francis, 2022/01/21
- [PULL 22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns, Alistair Francis, 2022/01/21
- [PULL 23/61] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns,
Alistair Francis <=
- [PULL 29/61] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V, Alistair Francis, 2022/01/21
- [PULL 19/61] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V, Alistair Francis, 2022/01/21
- [PULL 24/61] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns, Alistair Francis, 2022/01/21
- [PULL 25/61] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns, Alistair Francis, 2022/01/21
- [PULL 26/61] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns, Alistair Francis, 2022/01/21
- [PULL 28/61] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on, Alistair Francis, 2022/01/21
- [PULL 31/61] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns, Alistair Francis, 2022/01/21
- [PULL 27/61] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns, Alistair Francis, 2022/01/21
- [PULL 30/61] target/riscv: rvv-1.0: Add Zve32f support for configuration insns, Alistair Francis, 2022/01/21
- [PULL 32/61] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns, Alistair Francis, 2022/01/21