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[PATCH v6 2/7] target/arm: Make RVBAR available for all ARMv8 CPUs
From: |
tobias.roehmel |
Subject: |
[PATCH v6 2/7] target/arm: Make RVBAR available for all ARMv8 CPUs |
Date: |
Tue, 6 Dec 2022 11:24:59 +0100 |
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
RVBAR shadows RVBAR_ELx where x is the highest exception
level if the highest EL is not EL3. This patch also allows
ARMv8 CPUs to change the reset address with
the rvbar property.
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 6 +++++-
target/arm/helper.c | 21 ++++++++++++++-------
2 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 38d066c294..f9ab6af829 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -307,6 +307,10 @@ static void arm_cpu_reset(DeviceState *dev)
env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
CPACR, CP11, 3);
#endif
+ if (arm_feature(env, ARM_FEATURE_V8)) {
+ env->cp15.rvbar = cpu->rvbar_prop;
+ env->regs[15] = cpu->rvbar_prop;
+ }
}
#if defined(CONFIG_USER_ONLY)
@@ -1342,7 +1346,7 @@ void arm_cpu_post_init(Object *obj)
qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
}
- if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
object_property_add_uint64_ptr(obj, "rvbar",
&cpu->rvbar_prop,
OBJ_PROP_FLAG_READWRITE);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d857d61fa9..23a55dbe7d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7855,7 +7855,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (!arm_feature(env, ARM_FEATURE_EL3) &&
!arm_feature(env, ARM_FEATURE_EL2)) {
ARMCPRegInfo rvbar = {
- .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
+ .name = "RVBAR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
.access = PL1_R,
.fieldoffset = offsetof(CPUARMState, cp15.rvbar),
@@ -7946,13 +7946,20 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
/* RVBAR_EL2 is only implemented if EL2 is the highest EL */
if (!arm_feature(env, ARM_FEATURE_EL3)) {
- ARMCPRegInfo rvbar = {
- .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
- .access = PL2_R,
- .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+ ARMCPRegInfo rvbar[] = {
+ {
+ .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
+ .access = PL2_R,
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+ },
+ { .name = "RVBAR", .type = ARM_CP_ALIAS,
+ .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
+ .access = PL2_R,
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+ },
};
- define_one_arm_cp_reg(cpu, &rvbar);
+ define_arm_cp_regs(cpu, rvbar);
}
}
--
2.34.1
- [PATCH v6 0/7] Add ARM Cortex-R52 CPU, tobias.roehmel, 2022/12/06
- [PATCH v6 7/7] target/arm: Add ARM Cortex-R52 CPU, tobias.roehmel, 2022/12/06
- [PATCH v6 2/7] target/arm: Make RVBAR available for all ARMv8 CPUs,
tobias.roehmel <=
- [PATCH v6 1/7] target/arm: Don't add all MIDR aliases for cores that implement PMSA, tobias.roehmel, 2022/12/06
- [PATCH v6 3/7] target/arm: Make stage_2_format for cache attributes optional, tobias.roehmel, 2022/12/06
- [PATCH v6 5/7] target/arm: Add PMSAv8r registers, tobias.roehmel, 2022/12/06
- [PATCH v6 4/7] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32, tobias.roehmel, 2022/12/06
- [PATCH v6 6/7] target/arm: Add PMSAv8r functionality, tobias.roehmel, 2022/12/06
- Re: [PATCH v6 0/7] Add ARM Cortex-R52 CPU, Philippe Mathieu-Daudé, 2022/12/06
- Re: [PATCH v6 0/7] Add ARM Cortex-R52 CPU, Peter Maydell, 2022/12/19