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[PATCH v6 3/7] target/arm: Make stage_2_format for cache attributes opti
From: |
tobias.roehmel |
Subject: |
[PATCH v6 3/7] target/arm: Make stage_2_format for cache attributes optional |
Date: |
Tue, 6 Dec 2022 11:25:00 +0100 |
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
The v8R PMSAv8 has a two-stage MPU translation process, but, unlike
VMSAv8, the stage 2 attributes are in the same format as the stage 1
attributes (8-bit MAIR format). Rather than converting the MAIR
format to the format used for VMSA stage 2 (bits [5:2] of a VMSA
stage 2 descriptor) and then converting back to do the attribute
combination, allow combined_attrs_nofwb() to accept s2 attributes
that are already in the MAIR format.
We move the assert() to combined_attrs_fwb(), because that function
really does require a VMSA stage 2 attribute format. (We will never
get there for v8R, because PMSAv8 does not implement FEAT_S2FWB.)
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index f812734bfb..7d19829702 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2361,7 +2361,11 @@ static uint8_t combined_attrs_nofwb(uint64_t hcr,
{
uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs;
- s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs);
+ if (s2.is_s2_format) {
+ s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs);
+ } else {
+ s2_mair_attrs = s2.attrs;
+ }
s1lo = extract32(s1.attrs, 0, 4);
s2lo = extract32(s2_mair_attrs, 0, 4);
@@ -2418,6 +2422,8 @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr)
*/
static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2)
{
+ assert(s2.is_s2_format && !s1.is_s2_format);
+
switch (s2.attrs) {
case 7:
/* Use stage 1 attributes */
@@ -2467,7 +2473,7 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
ARMCacheAttrs ret;
bool tagged = false;
- assert(s2.is_s2_format && !s1.is_s2_format);
+ assert(!s1.is_s2_format);
ret.is_s2_format = false;
if (s1.attrs == 0xf0) {
--
2.34.1
- [PATCH v6 0/7] Add ARM Cortex-R52 CPU, tobias.roehmel, 2022/12/06
- [PATCH v6 7/7] target/arm: Add ARM Cortex-R52 CPU, tobias.roehmel, 2022/12/06
- [PATCH v6 2/7] target/arm: Make RVBAR available for all ARMv8 CPUs, tobias.roehmel, 2022/12/06
- [PATCH v6 1/7] target/arm: Don't add all MIDR aliases for cores that implement PMSA, tobias.roehmel, 2022/12/06
- [PATCH v6 3/7] target/arm: Make stage_2_format for cache attributes optional,
tobias.roehmel <=
- [PATCH v6 5/7] target/arm: Add PMSAv8r registers, tobias.roehmel, 2022/12/06
- [PATCH v6 4/7] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32, tobias.roehmel, 2022/12/06
- [PATCH v6 6/7] target/arm: Add PMSAv8r functionality, tobias.roehmel, 2022/12/06
- Re: [PATCH v6 0/7] Add ARM Cortex-R52 CPU, Philippe Mathieu-Daudé, 2022/12/06
- Re: [PATCH v6 0/7] Add ARM Cortex-R52 CPU, Peter Maydell, 2022/12/19