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Re: [PATCH v6 0/7] Add ARM Cortex-R52 CPU
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH v6 0/7] Add ARM Cortex-R52 CPU |
Date: |
Tue, 6 Dec 2022 11:39:33 +0100 |
User-agent: |
Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.5.1 |
On 6/12/22 11:24, tobias.roehmel@rwth-aachen.de wrote:
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
v6:
patch 5:
- I'm freeing the PRBAR/... strings explicitly now since
I don't know how to use autofree in this setup correctly.
Maybe {} around the part were the string is created/used,
such that it is dropped at }?
The pointer is declared outside of a for() statement. Then
inside this statement you alloc/free twice, using the same
pointer. This is correct. If you really want to use
g_autofree in such case, you'd need to declare within the
same statement, one pointer for each string:
for (i = 0; i < MIN(cpu->pmsav7_dregion, 32); ++i) {
uint8_t crm = 0b1000 | extract32(i, 1, 3);
uint8_t opc1 = extract32(i, 4, 1);
uint8_t opc2 = extract32(i, 0, 1) << 2;
g_autofree char *prbarn_str = g_strdup_printf("PRBAR%u", i);
g_autofree char *prlarn_str = g_strdup_printf("PRLAR%u", i);
const ARMCPRegInfo tmp_prbarn_reginfo = {
.name = prbarn_str, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW,
.cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
.access = PL1_RW, .resetvalue = 0,
.accessfn = access_tvm_trvm,
.writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
};
define_one_arm_cp_reg(cpu, &tmp_prbarn_reginfo);
opc2 = extract32(i, 0, 1) << 2 | 0x1;
const ARMCPRegInfo tmp_prlarn_reginfo = {
.name = prlarn_str, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW,
.cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
.access = PL1_RW, .resetvalue = 0,
.accessfn = access_tvm_trvm,
.writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
};
define_one_arm_cp_reg(cpu, &tmp_prlarn_reginfo);
}
(Note ARMCPRegInfo can be qualified const).
Regards,
Phil.
- [PATCH v6 0/7] Add ARM Cortex-R52 CPU, tobias.roehmel, 2022/12/06
- [PATCH v6 7/7] target/arm: Add ARM Cortex-R52 CPU, tobias.roehmel, 2022/12/06
- [PATCH v6 2/7] target/arm: Make RVBAR available for all ARMv8 CPUs, tobias.roehmel, 2022/12/06
- [PATCH v6 1/7] target/arm: Don't add all MIDR aliases for cores that implement PMSA, tobias.roehmel, 2022/12/06
- [PATCH v6 3/7] target/arm: Make stage_2_format for cache attributes optional, tobias.roehmel, 2022/12/06
- [PATCH v6 5/7] target/arm: Add PMSAv8r registers, tobias.roehmel, 2022/12/06
- [PATCH v6 4/7] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32, tobias.roehmel, 2022/12/06
- [PATCH v6 6/7] target/arm: Add PMSAv8r functionality, tobias.roehmel, 2022/12/06
- Re: [PATCH v6 0/7] Add ARM Cortex-R52 CPU,
Philippe Mathieu-Daudé <=
- Re: [PATCH v6 0/7] Add ARM Cortex-R52 CPU, Peter Maydell, 2022/12/19