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[PULL 18/45] hw/riscv: virt: Remove the redundant ipi-id property
From: |
Alistair Francis |
Subject: |
[PULL 18/45] hw/riscv: virt: Remove the redundant ipi-id property |
Date: |
Mon, 19 Dec 2022 12:16:36 +1000 |
From: Atish Patra <atishp@rivosinc.com>
The imsic DT binding[1] has changed and no longer require an ipi-id.
The latest IMSIC driver dynamically allocates ipi id if slow-ipi
is not defined.
Get rid of the unused dt property which may lead to confusion.
[1]
https://lore.kernel.org/lkml/20221111044207.1478350-5-apatel@ventanamicro.com/
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221122080529.1692533-1-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/virt.h | 1 -
hw/riscv/virt.c | 4 ----
2 files changed, 5 deletions(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index be4ab8fe7f..62513e075c 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -93,7 +93,6 @@ enum {
#define VIRT_PLATFORM_BUS_NUM_IRQS 32
-#define VIRT_IRQCHIP_IPI_MSI 1
#define VIRT_IRQCHIP_NUM_MSIS 255
#define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
#define VIRT_IRQCHIP_NUM_PRIO_BITS 3
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index a5bc7353b4..6cf9355b99 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -546,8 +546,6 @@ static void create_fdt_imsic(RISCVVirtState *s, const
MemMapEntry *memmap,
riscv_socket_count(mc) * sizeof(uint32_t) * 4);
qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
VIRT_IRQCHIP_NUM_MSIS);
- qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
- VIRT_IRQCHIP_IPI_MSI);
if (riscv_socket_count(mc) > 1) {
qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
imsic_num_bits(imsic_max_hart_per_socket));
@@ -597,8 +595,6 @@ static void create_fdt_imsic(RISCVVirtState *s, const
MemMapEntry *memmap,
riscv_socket_count(mc) * sizeof(uint32_t) * 4);
qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
VIRT_IRQCHIP_NUM_MSIS);
- qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
- VIRT_IRQCHIP_IPI_MSI);
if (imsic_guest_bits) {
qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
imsic_guest_bits);
--
2.38.1
- [PULL 08/45] hw/riscv/opentitan: add aon_timer base unimpl, (continued)
- [PULL 08/45] hw/riscv/opentitan: add aon_timer base unimpl, Alistair Francis, 2022/12/18
- [PULL 09/45] target/riscv: Add smstateen support, Alistair Francis, 2022/12/18
- [PULL 10/45] target/riscv: smstateen check for h/s/envcfg, Alistair Francis, 2022/12/18
- [PULL 11/45] target/riscv: generate virtual instruction exception, Alistair Francis, 2022/12/18
- [PULL 12/45] target/riscv: Add itrigger support when icount is not enabled, Alistair Francis, 2022/12/18
- [PULL 13/45] target/riscv: Add itrigger support when icount is enabled, Alistair Francis, 2022/12/18
- [PULL 14/45] target/riscv: Enable native debug itrigger, Alistair Francis, 2022/12/18
- [PULL 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState, Alistair Francis, 2022/12/18
- [PULL 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support, Alistair Francis, 2022/12/18
- [PULL 17/45] target/riscv: Typo fix in sstc() predicate, Alistair Francis, 2022/12/18
- [PULL 18/45] hw/riscv: virt: Remove the redundant ipi-id property,
Alistair Francis <=
- [PULL 27/45] target/riscv: Simplify helper_sret() a little bit, Alistair Francis, 2022/12/18
- [PULL 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state(), Alistair Francis, 2022/12/18
- [PULL 29/45] RISC-V: Add Zawrs ISA extension support, Alistair Francis, 2022/12/18
- [PULL 19/45] target/riscv: support cache-related PMU events in virtual mode, Alistair Francis, 2022/12/18
- [PULL 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+, Alistair Francis, 2022/12/18
- [PULL 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Alistair Francis, 2022/12/18
- [PULL 21/45] hw/misc: pfsoc: add fabric clocks to ioscb, Alistair Francis, 2022/12/18
- [PULL 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers, Alistair Francis, 2022/12/18
- [PULL 32/45] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC, Alistair Francis, 2022/12/18
- [PULL 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented, Alistair Francis, 2022/12/18