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[PULL 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for pr
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From: |
Alistair Francis |
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Subject: |
[PULL 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ |
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Date: |
Mon, 19 Dec 2022 12:16:46 +1000 |
From: Bin Meng <bmeng@tinylab.org>
Since priv spec v1.12, MRET and SRET now clear mstatus.MPRV when
leaving M-mode.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221207090037.281452-2-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/op_helper.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index a047d38152..878bcb03b8 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -154,6 +154,9 @@ target_ulong helper_sret(CPURISCVState *env)
get_field(mstatus, MSTATUS_SPIE));
mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
+ if (env->priv_ver >= PRIV_VERSION_1_12_0) {
+ mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
+ }
env->mstatus = mstatus;
if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
@@ -203,6 +206,9 @@ target_ulong helper_mret(CPURISCVState *env)
mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
mstatus = set_field(mstatus, MSTATUS_MPV, 0);
+ if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) {
+ mstatus = set_field(mstatus, MSTATUS_MPRV, 0);
+ }
env->mstatus = mstatus;
riscv_cpu_set_mode(env, prev_priv);
--
2.38.1
- [PULL 13/45] target/riscv: Add itrigger support when icount is enabled, (continued)
- [PULL 13/45] target/riscv: Add itrigger support when icount is enabled, Alistair Francis, 2022/12/18
- [PULL 14/45] target/riscv: Enable native debug itrigger, Alistair Francis, 2022/12/18
- [PULL 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState, Alistair Francis, 2022/12/18
- [PULL 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support, Alistair Francis, 2022/12/18
- [PULL 17/45] target/riscv: Typo fix in sstc() predicate, Alistair Francis, 2022/12/18
- [PULL 18/45] hw/riscv: virt: Remove the redundant ipi-id property, Alistair Francis, 2022/12/18
- [PULL 27/45] target/riscv: Simplify helper_sret() a little bit, Alistair Francis, 2022/12/18
- [PULL 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state(), Alistair Francis, 2022/12/18
- [PULL 29/45] RISC-V: Add Zawrs ISA extension support, Alistair Francis, 2022/12/18
- [PULL 19/45] target/riscv: support cache-related PMU events in virtual mode, Alistair Francis, 2022/12/18
- [PULL 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+,
Alistair Francis <=
- [PULL 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Alistair Francis, 2022/12/18
- [PULL 21/45] hw/misc: pfsoc: add fabric clocks to ioscb, Alistair Francis, 2022/12/18
- [PULL 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers, Alistair Francis, 2022/12/18
- [PULL 32/45] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC, Alistair Francis, 2022/12/18
- [PULL 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented, Alistair Francis, 2022/12/18
- [PULL 33/45] hw/riscv: Sort machines Kconfig options in alphabetical order, Alistair Francis, 2022/12/18
- [PULL 23/45] hw/{misc, riscv}: pfsoc: add system controller as unimplemented, Alistair Francis, 2022/12/18
- [PULL 34/45] hw/riscv: spike: Remove misleading comments, Alistair Francis, 2022/12/18
- [PULL 24/45] hw/intc: sifive_plic: fix out-of-bound access of source_priority array, Alistair Francis, 2022/12/18
- [PULL 35/45] hw/intc: sifive_plic: Drop PLICMode_H, Alistair Francis, 2022/12/18