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[PULL 27/45] target/riscv: Simplify helper_sret() a little bit
From: |
Alistair Francis |
Subject: |
[PULL 27/45] target/riscv: Simplify helper_sret() a little bit |
Date: |
Mon, 19 Dec 2022 12:16:45 +1000 |
From: Bin Meng <bmeng@tinylab.org>
There are 2 paths in helper_sret() and the same mstatus update codes
are replicated. Extract the common parts to simplify it a little bit.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221207090037.281452-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/op_helper.c | 20 ++++++--------------
1 file changed, 6 insertions(+), 14 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index d7af7f056b..a047d38152 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -149,21 +149,21 @@ target_ulong helper_sret(CPURISCVState *env)
}
mstatus = env->mstatus;
+ prev_priv = get_field(mstatus, MSTATUS_SPP);
+ mstatus = set_field(mstatus, MSTATUS_SIE,
+ get_field(mstatus, MSTATUS_SPIE));
+ mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
+ mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
+ env->mstatus = mstatus;
if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
/* We support Hypervisor extensions and virtulisation is disabled */
target_ulong hstatus = env->hstatus;
- prev_priv = get_field(mstatus, MSTATUS_SPP);
prev_virt = get_field(hstatus, HSTATUS_SPV);
hstatus = set_field(hstatus, HSTATUS_SPV, 0);
- mstatus = set_field(mstatus, MSTATUS_SPP, 0);
- mstatus = set_field(mstatus, SSTATUS_SIE,
- get_field(mstatus, SSTATUS_SPIE));
- mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
- env->mstatus = mstatus;
env->hstatus = hstatus;
if (prev_virt) {
@@ -171,14 +171,6 @@ target_ulong helper_sret(CPURISCVState *env)
}
riscv_cpu_set_virt_enabled(env, prev_virt);
- } else {
- prev_priv = get_field(mstatus, MSTATUS_SPP);
-
- mstatus = set_field(mstatus, MSTATUS_SIE,
- get_field(mstatus, MSTATUS_SPIE));
- mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
- mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
- env->mstatus = mstatus;
}
riscv_cpu_set_mode(env, prev_priv);
--
2.38.1
- [PULL 09/45] target/riscv: Add smstateen support, (continued)
- [PULL 09/45] target/riscv: Add smstateen support, Alistair Francis, 2022/12/18
- [PULL 10/45] target/riscv: smstateen check for h/s/envcfg, Alistair Francis, 2022/12/18
- [PULL 11/45] target/riscv: generate virtual instruction exception, Alistair Francis, 2022/12/18
- [PULL 12/45] target/riscv: Add itrigger support when icount is not enabled, Alistair Francis, 2022/12/18
- [PULL 13/45] target/riscv: Add itrigger support when icount is enabled, Alistair Francis, 2022/12/18
- [PULL 14/45] target/riscv: Enable native debug itrigger, Alistair Francis, 2022/12/18
- [PULL 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState, Alistair Francis, 2022/12/18
- [PULL 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support, Alistair Francis, 2022/12/18
- [PULL 17/45] target/riscv: Typo fix in sstc() predicate, Alistair Francis, 2022/12/18
- [PULL 18/45] hw/riscv: virt: Remove the redundant ipi-id property, Alistair Francis, 2022/12/18
- [PULL 27/45] target/riscv: Simplify helper_sret() a little bit,
Alistair Francis <=
- [PULL 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state(), Alistair Francis, 2022/12/18
- [PULL 29/45] RISC-V: Add Zawrs ISA extension support, Alistair Francis, 2022/12/18
- [PULL 19/45] target/riscv: support cache-related PMU events in virtual mode, Alistair Francis, 2022/12/18
- [PULL 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+, Alistair Francis, 2022/12/18
- [PULL 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Alistair Francis, 2022/12/18
- [PULL 21/45] hw/misc: pfsoc: add fabric clocks to ioscb, Alistair Francis, 2022/12/18
- [PULL 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers, Alistair Francis, 2022/12/18
- [PULL 32/45] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC, Alistair Francis, 2022/12/18
- [PULL 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented, Alistair Francis, 2022/12/18
- [PULL 33/45] hw/riscv: Sort machines Kconfig options in alphabetical order, Alistair Francis, 2022/12/18