[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cp
From: |
Alistair Francis |
Subject: |
[PULL 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state() |
Date: |
Mon, 19 Dec 2022 12:16:38 +1000 |
From: Bin Meng <bmeng@tinylab.org>
sstatus register dump is currently missing in riscv_cpu_dump_state().
As sstatus is a copy of mstatus, which is described in the priv spec,
it seems redundant to print the same information twice.
Add some comments for this to let people know this is intentional.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221125050354.3166023-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6fe176e483..b2c132e269 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -382,6 +382,10 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
int flags)
CSR_MHARTID,
CSR_MSTATUS,
CSR_MSTATUSH,
+ /*
+ * CSR_SSTATUS is intentionally omitted here as its value
+ * can be figured out by looking at CSR_MSTATUS
+ */
CSR_HSTATUS,
CSR_VSSTATUS,
CSR_MIP,
--
2.38.1
- [PULL 10/45] target/riscv: smstateen check for h/s/envcfg, (continued)
- [PULL 10/45] target/riscv: smstateen check for h/s/envcfg, Alistair Francis, 2022/12/18
- [PULL 11/45] target/riscv: generate virtual instruction exception, Alistair Francis, 2022/12/18
- [PULL 12/45] target/riscv: Add itrigger support when icount is not enabled, Alistair Francis, 2022/12/18
- [PULL 13/45] target/riscv: Add itrigger support when icount is enabled, Alistair Francis, 2022/12/18
- [PULL 14/45] target/riscv: Enable native debug itrigger, Alistair Francis, 2022/12/18
- [PULL 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState, Alistair Francis, 2022/12/18
- [PULL 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support, Alistair Francis, 2022/12/18
- [PULL 17/45] target/riscv: Typo fix in sstc() predicate, Alistair Francis, 2022/12/18
- [PULL 18/45] hw/riscv: virt: Remove the redundant ipi-id property, Alistair Francis, 2022/12/18
- [PULL 27/45] target/riscv: Simplify helper_sret() a little bit, Alistair Francis, 2022/12/18
- [PULL 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state(),
Alistair Francis <=
- [PULL 29/45] RISC-V: Add Zawrs ISA extension support, Alistair Francis, 2022/12/18
- [PULL 19/45] target/riscv: support cache-related PMU events in virtual mode, Alistair Francis, 2022/12/18
- [PULL 28/45] target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+, Alistair Francis, 2022/12/18
- [PULL 30/45] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Alistair Francis, 2022/12/18
- [PULL 21/45] hw/misc: pfsoc: add fabric clocks to ioscb, Alistair Francis, 2022/12/18
- [PULL 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers, Alistair Francis, 2022/12/18
- [PULL 32/45] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC, Alistair Francis, 2022/12/18
- [PULL 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented, Alistair Francis, 2022/12/18
- [PULL 33/45] hw/riscv: Sort machines Kconfig options in alphabetical order, Alistair Francis, 2022/12/18
- [PULL 23/45] hw/{misc, riscv}: pfsoc: add system controller as unimplemented, Alistair Francis, 2022/12/18