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[PULL v2 14/45] target/riscv: Enable native debug itrigger
From: |
Alistair Francis |
Subject: |
[PULL v2 14/45] target/riscv: Enable native debug itrigger |
Date: |
Thu, 22 Dec 2022 08:39:51 +1000 |
From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
When QEMU is not in icount mode, execute instruction one by one. The
tdata1 can be read directly.
When QEMU is in icount mode, use a timer to simulate the itrigger. The
tdata1 may be not right because of lazy update of count in tdata1. Thus,
We should pack the adjusted count into tdata1 before read it back.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221013062946.7530-4-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/debug.c | 72 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 371862cf38..b3574b250f 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -624,10 +624,80 @@ void riscv_itrigger_update_priv(CPURISCVState *env)
riscv_itrigger_update_count(env);
}
+static target_ulong itrigger_validate(CPURISCVState *env,
+ target_ulong ctrl)
+{
+ target_ulong val;
+
+ /* validate the generic part first */
+ val = tdata1_validate(env, ctrl, TRIGGER_TYPE_INST_CNT);
+
+ /* validate unimplemented (always zero) bits */
+ warn_always_zero_bit(ctrl, ITRIGGER_ACTION, "action");
+ warn_always_zero_bit(ctrl, ITRIGGER_HIT, "hit");
+ warn_always_zero_bit(ctrl, ITRIGGER_PENDING, "pending");
+
+ /* keep the mode and attribute bits */
+ val |= ctrl & (ITRIGGER_VU | ITRIGGER_VS | ITRIGGER_U | ITRIGGER_S |
+ ITRIGGER_M | ITRIGGER_COUNT);
+
+ return val;
+}
+
+static void itrigger_reg_write(CPURISCVState *env, target_ulong index,
+ int tdata_index, target_ulong val)
+{
+ target_ulong new_val;
+
+ switch (tdata_index) {
+ case TDATA1:
+ /* set timer for icount */
+ new_val = itrigger_validate(env, val);
+ if (new_val != env->tdata1[index]) {
+ env->tdata1[index] = new_val;
+ if (icount_enabled()) {
+ env->last_icount = icount_get_raw();
+ /* set the count to timer */
+ timer_mod(env->itrigger_timer[index],
+ env->last_icount + itrigger_get_count(env, index));
+ }
+ }
+ break;
+ case TDATA2:
+ qemu_log_mask(LOG_UNIMP,
+ "tdata2 is not supported for icount trigger\n");
+ break;
+ case TDATA3:
+ qemu_log_mask(LOG_UNIMP,
+ "tdata3 is not supported for icount trigger\n");
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ return;
+}
+
+static int itrigger_get_adjust_count(CPURISCVState *env)
+{
+ int count = itrigger_get_count(env, env->trigger_cur), executed;
+ if ((count != 0) && check_itrigger_priv(env, env->trigger_cur)) {
+ executed = icount_get_raw() - env->last_icount;
+ count += executed;
+ }
+ return count;
+}
+
target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
{
+ int trigger_type;
switch (tdata_index) {
case TDATA1:
+ trigger_type = extract_trigger_type(env,
env->tdata1[env->trigger_cur]);
+ if ((trigger_type == TRIGGER_TYPE_INST_CNT) && icount_enabled()) {
+ return deposit64(env->tdata1[env->trigger_cur], 10, 14,
+ itrigger_get_adjust_count(env));
+ }
return env->tdata1[env->trigger_cur];
case TDATA2:
return env->tdata2[env->trigger_cur];
@@ -656,6 +726,8 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index,
target_ulong val)
type6_reg_write(env, env->trigger_cur, tdata_index, val);
break;
case TRIGGER_TYPE_INST_CNT:
+ itrigger_reg_write(env, env->trigger_cur, tdata_index, val);
+ break;
case TRIGGER_TYPE_INT:
case TRIGGER_TYPE_EXCP:
case TRIGGER_TYPE_EXT_SRC:
--
2.38.1
- [PULL v2 03/45] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro, (continued)
- [PULL v2 03/45] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro, Alistair Francis, 2022/12/21
- [PULL v2 04/45] tcg/riscv: Fix range matched by TCG_CT_CONST_M12, Alistair Francis, 2022/12/21
- [PULL v2 08/45] hw/riscv/opentitan: add aon_timer base unimpl, Alistair Francis, 2022/12/21
- [PULL v2 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st, Alistair Francis, 2022/12/21
- [PULL v2 07/45] hw/riscv/opentitan: bump opentitan, Alistair Francis, 2022/12/21
- [PULL v2 10/45] target/riscv: smstateen check for h/s/envcfg, Alistair Francis, 2022/12/21
- [PULL v2 09/45] target/riscv: Add smstateen support, Alistair Francis, 2022/12/21
- [PULL v2 11/45] target/riscv: generate virtual instruction exception, Alistair Francis, 2022/12/21
- [PULL v2 13/45] target/riscv: Add itrigger support when icount is enabled, Alistair Francis, 2022/12/21
- [PULL v2 12/45] target/riscv: Add itrigger support when icount is not enabled, Alistair Francis, 2022/12/21
- [PULL v2 14/45] target/riscv: Enable native debug itrigger,
Alistair Francis <=
- [PULL v2 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState, Alistair Francis, 2022/12/21
- [PULL v2 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support, Alistair Francis, 2022/12/21
- [PULL v2 17/45] target/riscv: Typo fix in sstc() predicate, Alistair Francis, 2022/12/21
- [PULL v2 18/45] hw/riscv: virt: Remove the redundant ipi-id property, Alistair Francis, 2022/12/21
- [PULL v2 19/45] target/riscv: support cache-related PMU events in virtual mode, Alistair Francis, 2022/12/21
- [PULL v2 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state(), Alistair Francis, 2022/12/21
- [PULL v2 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented, Alistair Francis, 2022/12/21
- [PULL v2 21/45] hw/misc: pfsoc: add fabric clocks to ioscb, Alistair Francis, 2022/12/21
- [PULL v2 23/45] hw/{misc, riscv}: pfsoc: add system controller as unimplemented, Alistair Francis, 2022/12/21
- [PULL v2 24/45] hw/intc: sifive_plic: fix out-of-bound access of source_priority array, Alistair Francis, 2022/12/21