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[PULL v2 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa suppo
From: |
Alistair Francis |
Subject: |
[PULL v2 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support |
Date: |
Thu, 22 Dec 2022 08:39:53 +1000 |
From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Commit 40244040a7a changed the way the S irqs are numbered. This breaks when
using numa configuration, e.g.:
./qemu-system-riscv64 -nographic -machine virt,dumpdtb=numa-tree.dtb \
-m 2G -smp cpus=16 \
-object memory-backend-ram,id=mem0,size=512M \
-object memory-backend-ram,id=mem1,size=512M \
-object memory-backend-ram,id=mem2,size=512M \
-object memory-backend-ram,id=mem3,size=512M \
-numa node,cpus=0-3,memdev=mem0,nodeid=0 \
-numa node,cpus=4-7,memdev=mem1,nodeid=1 \
-numa node,cpus=8-11,memdev=mem2,nodeid=2 \
-numa node,cpus=12-15,memdev=mem3,nodeid=3
leads to:
Unexpected error in object_property_find_err() at ../qom/object.c:1304:
qemu-system-riscv64: Property 'riscv.sifive.plic.unnamed-gpio-out[8]' not
found
This patch makes the nubering of the S irqs identical to what it was before.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Message-Id: <20221114135122.1668703-1-frederic.petrot@univ-grenoble-alpes.fr>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/sifive_plic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index c2dfacf028..b4949bef97 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -476,11 +476,11 @@ DeviceState *sifive_plic_create(hwaddr addr, char
*hart_config,
CPUState *cpu = qemu_get_cpu(cpu_num);
if (plic->addr_config[i].mode == PLICMode_M) {
- qdev_connect_gpio_out(dev, num_harts - plic->hartid_base + cpu_num,
+ qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts,
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
}
if (plic->addr_config[i].mode == PLICMode_S) {
- qdev_connect_gpio_out(dev, cpu_num,
+ qdev_connect_gpio_out(dev, cpu_num - hartid_base,
qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
}
}
--
2.38.1
- [PULL v2 08/45] hw/riscv/opentitan: add aon_timer base unimpl, (continued)
- [PULL v2 08/45] hw/riscv/opentitan: add aon_timer base unimpl, Alistair Francis, 2022/12/21
- [PULL v2 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st, Alistair Francis, 2022/12/21
- [PULL v2 07/45] hw/riscv/opentitan: bump opentitan, Alistair Francis, 2022/12/21
- [PULL v2 10/45] target/riscv: smstateen check for h/s/envcfg, Alistair Francis, 2022/12/21
- [PULL v2 09/45] target/riscv: Add smstateen support, Alistair Francis, 2022/12/21
- [PULL v2 11/45] target/riscv: generate virtual instruction exception, Alistair Francis, 2022/12/21
- [PULL v2 13/45] target/riscv: Add itrigger support when icount is enabled, Alistair Francis, 2022/12/21
- [PULL v2 12/45] target/riscv: Add itrigger support when icount is not enabled, Alistair Francis, 2022/12/21
- [PULL v2 14/45] target/riscv: Enable native debug itrigger, Alistair Francis, 2022/12/21
- [PULL v2 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState, Alistair Francis, 2022/12/21
- [PULL v2 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support,
Alistair Francis <=
- [PULL v2 17/45] target/riscv: Typo fix in sstc() predicate, Alistair Francis, 2022/12/21
- [PULL v2 18/45] hw/riscv: virt: Remove the redundant ipi-id property, Alistair Francis, 2022/12/21
- [PULL v2 19/45] target/riscv: support cache-related PMU events in virtual mode, Alistair Francis, 2022/12/21
- [PULL v2 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state(), Alistair Francis, 2022/12/21
- [PULL v2 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented, Alistair Francis, 2022/12/21
- [PULL v2 21/45] hw/misc: pfsoc: add fabric clocks to ioscb, Alistair Francis, 2022/12/21
- [PULL v2 23/45] hw/{misc, riscv}: pfsoc: add system controller as unimplemented, Alistair Francis, 2022/12/21
- [PULL v2 24/45] hw/intc: sifive_plic: fix out-of-bound access of source_priority array, Alistair Francis, 2022/12/21
- [PULL v2 25/45] target/riscv: Fix mret exception cause when no pmp rule is configured, Alistair Francis, 2022/12/21
- [PULL v2 26/45] target/riscv: Set pc_succ_insn for !rvc illegal insn, Alistair Francis, 2022/12/21