[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v2 17/45] target/riscv: Typo fix in sstc() predicate
From: |
Alistair Francis |
Subject: |
[PULL v2 17/45] target/riscv: Typo fix in sstc() predicate |
Date: |
Thu, 22 Dec 2022 08:39:54 +1000 |
From: Anup Patel <apatel@ventanamicro.com>
We should use "&&" instead of "&" when checking hcounteren.TM and
henvcfg.STCE bits.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221108125703.1463577-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 71236f2b5d..0db2c233e5 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -940,7 +940,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
}
if (riscv_cpu_virt_enabled(env)) {
- if (!(get_field(env->hcounteren, COUNTEREN_TM) &
+ if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
get_field(env->henvcfg, HENVCFG_STCE))) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
--
2.38.1
- [PULL v2 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st, (continued)
- [PULL v2 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st, Alistair Francis, 2022/12/21
- [PULL v2 07/45] hw/riscv/opentitan: bump opentitan, Alistair Francis, 2022/12/21
- [PULL v2 10/45] target/riscv: smstateen check for h/s/envcfg, Alistair Francis, 2022/12/21
- [PULL v2 09/45] target/riscv: Add smstateen support, Alistair Francis, 2022/12/21
- [PULL v2 11/45] target/riscv: generate virtual instruction exception, Alistair Francis, 2022/12/21
- [PULL v2 13/45] target/riscv: Add itrigger support when icount is enabled, Alistair Francis, 2022/12/21
- [PULL v2 12/45] target/riscv: Add itrigger support when icount is not enabled, Alistair Francis, 2022/12/21
- [PULL v2 14/45] target/riscv: Enable native debug itrigger, Alistair Francis, 2022/12/21
- [PULL v2 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState, Alistair Francis, 2022/12/21
- [PULL v2 16/45] hw/intc: sifive_plic: Renumber the S irqs for numa support, Alistair Francis, 2022/12/21
- [PULL v2 17/45] target/riscv: Typo fix in sstc() predicate,
Alistair Francis <=
- [PULL v2 18/45] hw/riscv: virt: Remove the redundant ipi-id property, Alistair Francis, 2022/12/21
- [PULL v2 19/45] target/riscv: support cache-related PMU events in virtual mode, Alistair Francis, 2022/12/21
- [PULL v2 20/45] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state(), Alistair Francis, 2022/12/21
- [PULL v2 22/45] hw/riscv: pfsoc: add missing FICs as unimplemented, Alistair Francis, 2022/12/21
- [PULL v2 21/45] hw/misc: pfsoc: add fabric clocks to ioscb, Alistair Francis, 2022/12/21
- [PULL v2 23/45] hw/{misc, riscv}: pfsoc: add system controller as unimplemented, Alistair Francis, 2022/12/21
- [PULL v2 24/45] hw/intc: sifive_plic: fix out-of-bound access of source_priority array, Alistair Francis, 2022/12/21
- [PULL v2 25/45] target/riscv: Fix mret exception cause when no pmp rule is configured, Alistair Francis, 2022/12/21
- [PULL v2 26/45] target/riscv: Set pc_succ_insn for !rvc illegal insn, Alistair Francis, 2022/12/21
- [PULL v2 27/45] target/riscv: Simplify helper_sret() a little bit, Alistair Francis, 2022/12/21