[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC PATCH 39/43] target/loongarch: Implement vinsgr2vr vpickve2gr vrepl
|
From: |
Song Gao |
|
Subject: |
[RFC PATCH 39/43] target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr |
|
Date: |
Sat, 24 Dec 2022 16:16:29 +0800 |
This patch includes:
- VINSGR2VR.{B/H/W/D};
- VPICKVE2GR.{B/H/W/D}[U];
- VREPLGR2VR.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/disas.c | 33 +++++
target/loongarch/helper.h | 18 +++
target/loongarch/insn_trans/trans_lsx.c.inc | 53 +++++++
target/loongarch/insns.decode | 30 ++++
target/loongarch/lsx_helper.c | 154 ++++++++++++++++++++
5 files changed, 288 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 88e6ed1eef..2f7c726158 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -789,6 +789,21 @@ static void output_vvvv(DisasContext *ctx, arg_vvvv *a,
const char *mnemonic)
output(ctx, mnemonic, "v%d, v%d, v%d, v%d", a->vd, a->vj, a->vk, a->va);
}
+static void output_vr_i(DisasContext *ctx, arg_vr_i *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "v%d, r%d, 0x%x", a->vd, a->rj, a->imm);
+}
+
+static void output_rv_i(DisasContext *ctx, arg_rv_i *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "r%d, v%d, 0x%x", a->rd, a->vj, a->imm);
+}
+
+static void output_vr(DisasContext *ctx, arg_vr *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "v%d, r%d", a->vd, a->rj);
+}
+
INSN_LSX(vadd_b, vvv)
INSN_LSX(vadd_h, vvv)
INSN_LSX(vadd_w, vvv)
@@ -1532,3 +1547,21 @@ INSN_LSX(vsetallnez_b, cv)
INSN_LSX(vsetallnez_h, cv)
INSN_LSX(vsetallnez_w, cv)
INSN_LSX(vsetallnez_d, cv)
+
+INSN_LSX(vinsgr2vr_b, vr_i)
+INSN_LSX(vinsgr2vr_h, vr_i)
+INSN_LSX(vinsgr2vr_w, vr_i)
+INSN_LSX(vinsgr2vr_d, vr_i)
+INSN_LSX(vpickve2gr_b, rv_i)
+INSN_LSX(vpickve2gr_h, rv_i)
+INSN_LSX(vpickve2gr_w, rv_i)
+INSN_LSX(vpickve2gr_d, rv_i)
+INSN_LSX(vpickve2gr_bu, rv_i)
+INSN_LSX(vpickve2gr_hu, rv_i)
+INSN_LSX(vpickve2gr_wu, rv_i)
+INSN_LSX(vpickve2gr_du, rv_i)
+
+INSN_LSX(vreplgr2vr_b, vr)
+INSN_LSX(vreplgr2vr_h, vr)
+INSN_LSX(vreplgr2vr_w, vr)
+INSN_LSX(vreplgr2vr_d, vr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 1bef2a901f..00570221c7 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -791,3 +791,21 @@ DEF_HELPER_3(vsetallnez_b, void, env, i32, i32)
DEF_HELPER_3(vsetallnez_h, void, env, i32, i32)
DEF_HELPER_3(vsetallnez_w, void, env, i32, i32)
DEF_HELPER_3(vsetallnez_d, void, env, i32, i32)
+
+DEF_HELPER_4(vinsgr2vr_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vinsgr2vr_h, void, env, i32, i32, i32)
+DEF_HELPER_4(vinsgr2vr_w, void, env, i32, i32, i32)
+DEF_HELPER_4(vinsgr2vr_d, void, env, i32, i32, i32)
+DEF_HELPER_4(vpickve2gr_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vpickve2gr_h, void, env, i32, i32, i32)
+DEF_HELPER_4(vpickve2gr_w, void, env, i32, i32, i32)
+DEF_HELPER_4(vpickve2gr_d, void, env, i32, i32, i32)
+DEF_HELPER_4(vpickve2gr_bu, void, env, i32, i32, i32)
+DEF_HELPER_4(vpickve2gr_hu, void, env, i32, i32, i32)
+DEF_HELPER_4(vpickve2gr_wu, void, env, i32, i32, i32)
+DEF_HELPER_4(vpickve2gr_du, void, env, i32, i32, i32)
+
+DEF_HELPER_3(vreplgr2vr_b, void, env, i32, i32)
+DEF_HELPER_3(vreplgr2vr_h, void, env, i32, i32)
+DEF_HELPER_3(vreplgr2vr_w, void, env, i32, i32)
+DEF_HELPER_3(vreplgr2vr_d, void, env, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc
b/target/loongarch/insn_trans/trans_lsx.c.inc
index 7bf7f33724..c753e61b4c 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -75,6 +75,41 @@ static bool gen_vvvv(DisasContext *ctx, arg_vvvv *a,
return true;
}
+static bool gen_vr_i(DisasContext *ctx, arg_vr_i *a,
+ void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 vd = tcg_constant_i32(a->vd);
+ TCGv_i32 rj = tcg_constant_i32(a->rj);
+ TCGv_i32 imm = tcg_constant_i32(a->imm);
+
+ CHECK_SXE;
+ func(cpu_env, vd, rj, imm);
+ return true;
+}
+
+static bool gen_rv_i(DisasContext *ctx, arg_rv_i *a,
+ void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 rd = tcg_constant_i32(a->rd);
+ TCGv_i32 vj = tcg_constant_i32(a->vj);
+ TCGv_i32 imm = tcg_constant_i32(a->imm);
+
+ CHECK_SXE;
+ func(cpu_env, rd, vj, imm);
+ return true;
+}
+
+static bool gen_vr(DisasContext *ctx, arg_vr *a,
+ void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 vd = tcg_constant_i32(a->vd);
+ TCGv_i32 rj = tcg_constant_i32(a->rj);
+
+ CHECK_SXE;
+ func(cpu_env, vd, rj);
+ return true;
+}
+
TRANS(vadd_b, gen_vvv, gen_helper_vadd_b)
TRANS(vadd_h, gen_vvv, gen_helper_vadd_h)
TRANS(vadd_w, gen_vvv, gen_helper_vadd_w)
@@ -753,3 +788,21 @@ TRANS(vsetallnez_b, gen_cv, gen_helper_vsetallnez_b)
TRANS(vsetallnez_h, gen_cv, gen_helper_vsetallnez_h)
TRANS(vsetallnez_w, gen_cv, gen_helper_vsetallnez_w)
TRANS(vsetallnez_d, gen_cv, gen_helper_vsetallnez_d)
+
+TRANS(vinsgr2vr_b, gen_vr_i, gen_helper_vinsgr2vr_b)
+TRANS(vinsgr2vr_h, gen_vr_i, gen_helper_vinsgr2vr_h)
+TRANS(vinsgr2vr_w, gen_vr_i, gen_helper_vinsgr2vr_w)
+TRANS(vinsgr2vr_d, gen_vr_i, gen_helper_vinsgr2vr_d)
+TRANS(vpickve2gr_b, gen_rv_i, gen_helper_vpickve2gr_b)
+TRANS(vpickve2gr_h, gen_rv_i, gen_helper_vpickve2gr_h)
+TRANS(vpickve2gr_w, gen_rv_i, gen_helper_vpickve2gr_w)
+TRANS(vpickve2gr_d, gen_rv_i, gen_helper_vpickve2gr_d)
+TRANS(vpickve2gr_bu, gen_rv_i, gen_helper_vpickve2gr_bu)
+TRANS(vpickve2gr_hu, gen_rv_i, gen_helper_vpickve2gr_hu)
+TRANS(vpickve2gr_wu, gen_rv_i, gen_helper_vpickve2gr_wu)
+TRANS(vpickve2gr_du, gen_rv_i, gen_helper_vpickve2gr_du)
+
+TRANS(vreplgr2vr_b, gen_vr, gen_helper_vreplgr2vr_b)
+TRANS(vreplgr2vr_h, gen_vr, gen_helper_vreplgr2vr_h)
+TRANS(vreplgr2vr_w, gen_vr, gen_helper_vreplgr2vr_w)
+TRANS(vreplgr2vr_d, gen_vr, gen_helper_vreplgr2vr_d)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index fb1cc29aff..45eff88830 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -495,6 +495,9 @@ dbcl 0000 00000010 10101 ...............
@i15
&vv_i vd vj imm
&vvvv vd vj vk va
&vvv_fcond vd vj vk fcond
+&vr_i vd rj imm
+&rv_i rd vj imm
+&vr vd rj
#
# LSX Formats
@@ -511,6 +514,15 @@ dbcl 0000 00000010 10101 ...............
@i15
@vv_i5 .... ........ ..... imm:s5 vj:5 vd:5 &vv_i
@vvvv .... ........ va:5 vk:5 vj:5 vd:5 &vvvv
@vvv_fcond .... ........ fcond:5 vk:5 vj:5 vd:5 &vvv_fcond
+@vr_ui4 .... ........ ..... . imm:4 rj:5 vd:5 &vr_i
+@vr_ui3 .... ........ ..... .. imm:3 rj:5 vd:5 &vr_i
+@vr_ui2 .... ........ ..... ... imm:2 rj:5 vd:5 &vr_i
+@vr_ui1 .... ........ ..... .... imm:1 rj:5 vd:5 &vr_i
+@rv_ui4 .... ........ ..... . imm:4 vj:5 rd:5 &rv_i
+@rv_ui3 .... ........ ..... .. imm:3 vj:5 rd:5 &rv_i
+@rv_ui2 .... ........ ..... ... imm:2 vj:5 rd:5 &rv_i
+@rv_ui1 .... ........ ..... .... imm:1 vj:5 rd:5 &rv_i
+@vr .... ........ ..... ..... rj:5 vd:5 &vr
vadd_b 0111 00000000 10100 ..... ..... ..... @vvv
vadd_h 0111 00000000 10101 ..... ..... ..... @vvv
@@ -1166,3 +1178,21 @@ vsetallnez_b 0111 00101001 11001 01100 ..... 00 ...
@cv
vsetallnez_h 0111 00101001 11001 01101 ..... 00 ... @cv
vsetallnez_w 0111 00101001 11001 01110 ..... 00 ... @cv
vsetallnez_d 0111 00101001 11001 01111 ..... 00 ... @cv
+
+vinsgr2vr_b 0111 00101110 10111 0 .... ..... ..... @vr_ui4
+vinsgr2vr_h 0111 00101110 10111 10 ... ..... ..... @vr_ui3
+vinsgr2vr_w 0111 00101110 10111 110 .. ..... ..... @vr_ui2
+vinsgr2vr_d 0111 00101110 10111 1110 . ..... ..... @vr_ui1
+vpickve2gr_b 0111 00101110 11111 0 .... ..... ..... @rv_ui4
+vpickve2gr_h 0111 00101110 11111 10 ... ..... ..... @rv_ui3
+vpickve2gr_w 0111 00101110 11111 110 .. ..... ..... @rv_ui2
+vpickve2gr_d 0111 00101110 11111 1110 . ..... ..... @rv_ui1
+vpickve2gr_bu 0111 00101111 00111 0 .... ..... ..... @rv_ui4
+vpickve2gr_hu 0111 00101111 00111 10 ... ..... ..... @rv_ui3
+vpickve2gr_wu 0111 00101111 00111 110 .. ..... ..... @rv_ui2
+vpickve2gr_du 0111 00101111 00111 1110 . ..... ..... @rv_ui1
+
+vreplgr2vr_b 0111 00101001 11110 00000 ..... ..... @vr
+vreplgr2vr_h 0111 00101001 11110 00001 ..... ..... @vr
+vreplgr2vr_w 0111 00101001 11110 00010 ..... ..... @vr
+vreplgr2vr_d 0111 00101001 11110 00011 ..... ..... @vr
diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c
index f4cdfae87a..15dbf4fc32 100644
--- a/target/loongarch/lsx_helper.c
+++ b/target/loongarch/lsx_helper.c
@@ -35,6 +35,21 @@
void helper_##NAME(CPULoongArchState *env, uint32_t cd, uint32_t vj) \
{ FUNC(env, cd, vj, BIT, __VA_ARGS__); }
+#define DO_HELPER_VR_I(NAME, BIT, FUNC, ...) \
+ void helper_##NAME(CPULoongArchState *env, \
+ uint32_t vd, uint32_t rj, uint32_t imm) \
+ { FUNC(env, vd, rj, imm, BIT, __VA_ARGS__ ); }
+
+#define DO_HELPER_RV_I(NAME, BIT, FUNC, ...) \
+ void helper_##NAME(CPULoongArchState *env, \
+ uint32_t rd, uint32_t vj, uint32_t imm) \
+ { FUNC(env, rd, vj, imm, BIT, __VA_ARGS__ ); }
+
+#define DO_HELPER_VR(NAME, BIT, FUNC, ...) \
+ void helper_##NAME(CPULoongArchState *env, \
+ uint32_t vd, uint32_t rj) \
+ { FUNC(env, vd, rj, BIT, __VA_ARGS__ ); }
+
static void helper_vvv(CPULoongArchState *env,
uint32_t vd, uint32_t vj, uint32_t vk, int bit,
void (*func)(vec_t*, vec_t*, vec_t*, int, int))
@@ -4391,3 +4406,142 @@ DO_HELPER_CV(vsetallnez_b, 8, helper_setallnez,
do_setallnez)
DO_HELPER_CV(vsetallnez_h, 16, helper_setallnez, do_setallnez)
DO_HELPER_CV(vsetallnez_w, 32, helper_setallnez, do_setallnez)
DO_HELPER_CV(vsetallnez_d, 64, helper_setallnez, do_setallnez)
+
+static void helper_vr_i(CPULoongArchState *env,
+ uint32_t vd, uint32_t rj, uint32_t imm, int bit,
+ void (*func)(vec_t*, uint64_t, uint32_t, int))
+{
+ vec_t *Vd = &(env->fpr[vd].vec);
+ uint64_t Rj = env->gpr[rj];
+
+ imm %= (LSX_LEN/bit);
+
+ func(Vd, Rj, imm, bit);
+}
+
+static void do_insgr2vr(vec_t *Vd, uint64_t value, uint32_t imm, int bit)
+{
+ switch (bit) {
+ case 8:
+ Vd->B[imm] = (int8_t)value;
+ break;
+ case 16:
+ Vd->H[imm] = (int16_t)value;
+ break;
+ case 32:
+ Vd->W[imm] = (int32_t)value;
+ break;
+ case 64:
+ Vd->D[imm] = (int64_t)value;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+DO_HELPER_VR_I(vinsgr2vr_b, 8, helper_vr_i, do_insgr2vr)
+DO_HELPER_VR_I(vinsgr2vr_h, 16, helper_vr_i, do_insgr2vr)
+DO_HELPER_VR_I(vinsgr2vr_w, 32, helper_vr_i, do_insgr2vr)
+DO_HELPER_VR_I(vinsgr2vr_d, 64, helper_vr_i, do_insgr2vr)
+
+static void helper_rv_i(CPULoongArchState *env,
+ uint32_t rd, uint32_t vj, uint32_t imm, int bit,
+ void (*func)(CPULoongArchState*, uint32_t, vec_t*,
+ uint32_t, int))
+{
+ vec_t *Vj = &(env->fpr[vj].vec);
+
+ imm %=(LSX_LEN/bit);
+
+ func(env, rd, Vj, imm, bit);
+}
+
+static void do_pickve2gr_s(CPULoongArchState *env,
+ uint32_t rd, vec_t *Vj, uint32_t imm, int bit)
+{
+ switch (bit) {
+ case 8:
+ env->gpr[rd] = Vj->B[imm];
+ break;
+ case 16:
+ env->gpr[rd] = Vj->H[imm];
+ break;
+ case 32:
+ env->gpr[rd] = Vj->W[imm];
+ break;
+ case 64:
+ env->gpr[rd] = Vj->D[imm];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void do_pickve2gr_u(CPULoongArchState *env,
+ uint32_t rd, vec_t *Vj, uint32_t imm, int bit)
+{
+ switch (bit) {
+ case 8:
+ env->gpr[rd] = (uint8_t)Vj->B[imm];
+ break;
+ case 16:
+ env->gpr[rd] = (uint16_t)Vj->H[imm];
+ break;
+ case 32:
+ env->gpr[rd] = (uint32_t)Vj->W[imm];
+ break;
+ case 64:
+ env->gpr[rd] = (uint64_t)Vj->D[imm];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+DO_HELPER_RV_I(vpickve2gr_b, 8, helper_rv_i, do_pickve2gr_s)
+DO_HELPER_RV_I(vpickve2gr_h, 16, helper_rv_i, do_pickve2gr_s)
+DO_HELPER_RV_I(vpickve2gr_w, 32, helper_rv_i, do_pickve2gr_s)
+DO_HELPER_RV_I(vpickve2gr_d, 64, helper_rv_i, do_pickve2gr_s)
+DO_HELPER_RV_I(vpickve2gr_bu, 8, helper_rv_i, do_pickve2gr_u)
+DO_HELPER_RV_I(vpickve2gr_hu, 16, helper_rv_i, do_pickve2gr_u)
+DO_HELPER_RV_I(vpickve2gr_wu, 32, helper_rv_i, do_pickve2gr_u)
+DO_HELPER_RV_I(vpickve2gr_du, 64, helper_rv_i, do_pickve2gr_u)
+
+static void helper_vr(CPULoongArchState *env,
+ uint32_t vd, uint32_t rj, int bit,
+ void (*func)(CPULoongArchState*,
+ vec_t*, uint32_t, int, int))
+{
+ int i;
+ vec_t *Vd = &(env->fpr[vd].vec);
+
+ for (i = 0; i < LSX_LEN/bit; i++) {
+ func(env, Vd, rj, bit, i);
+ }
+}
+
+static void do_replgr2vr(CPULoongArchState *env,
+ vec_t *Vd, uint32_t rj, int bit, int n)
+{
+ switch (bit) {
+ case 8:
+ Vd->B[n] = (int8_t)env->gpr[rj];
+ break;
+ case 16:
+ Vd->H[n] = (int16_t)env->gpr[rj];
+ break;
+ case 32:
+ Vd->W[n] = (int32_t)env->gpr[rj];
+ break;
+ case 64:
+ Vd->D[n] = (int64_t)env->gpr[rj];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+DO_HELPER_VR(vreplgr2vr_b, 8, helper_vr, do_replgr2vr)
+DO_HELPER_VR(vreplgr2vr_h, 16, helper_vr, do_replgr2vr)
+DO_HELPER_VR(vreplgr2vr_w, 32, helper_vr, do_replgr2vr)
+DO_HELPER_VR(vreplgr2vr_d, 64, helper_vr, do_replgr2vr)
--
2.31.1
- [RFC PATCH 29/43] target/loongarch: Implement vssrlrn vssrarn, (continued)
- [RFC PATCH 29/43] target/loongarch: Implement vssrlrn vssrarn, Song Gao, 2022/12/24
- [RFC PATCH 33/43] target/loongarch: Implement vfrstp, Song Gao, 2022/12/24
- [RFC PATCH 26/43] target/loongarch: Implement vsrln vsran, Song Gao, 2022/12/24
- [RFC PATCH 23/43] target/loongarch: Implement vsll vsrl vsra vrotr, Song Gao, 2022/12/24
- [RFC PATCH 27/43] target/loongarch: Implement vsrlrn vsrarn, Song Gao, 2022/12/24
- [RFC PATCH 30/43] target/loongarch: Implement vclo vclz, Song Gao, 2022/12/24
- [RFC PATCH 38/43] target/loongarch: Implement vbitsel vset, Song Gao, 2022/12/24
- [RFC PATCH 35/43] target/loongarch: Implement LSX fpu fcvt instructions, Song Gao, 2022/12/24
- [RFC PATCH 39/43] target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr,
Song Gao <=
- [RFC PATCH 41/43] target/loongarch: Implement vilvl vilvh vextrins vshuf, Song Gao, 2022/12/24
- [RFC PATCH 42/43] target/loongarch: Implement vld vst, Song Gao, 2022/12/24
- [RFC PATCH 43/43] target/loongarch: Implement vldi, Song Gao, 2022/12/24
- [RFC PATCH 18/43] target/loongarch: Implement vsat, Song Gao, 2022/12/24
- [RFC PATCH 19/43] target/loongarch: Implement vexth, Song Gao, 2022/12/24
- [RFC PATCH 31/43] target/loongarch: Implement vpcnt, Song Gao, 2022/12/24