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[PATCH v3 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU runnin
From: |
LIU Zhiwei |
Subject: |
[PATCH v3 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 |
Date: |
Wed, 3 Jul 2024 22:49:16 +0800 |
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure pmp_size is correctly determined using mxl for RV32
in RV64 QEMU.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 9eea397e72..f65aa3dba7 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -326,7 +326,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
*/
pmp_size = -(addr | TARGET_PAGE_MASK);
} else {
- pmp_size = sizeof(target_ulong);
+ pmp_size = 2UL << riscv_cpu_mxl(env);
}
} else {
pmp_size = size;
--
2.25.1
- [PATCH v3 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU, LIU Zhiwei, 2024/07/03
- [PATCH v3 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI, LIU Zhiwei, 2024/07/03
- [PATCH v3 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32,
LIU Zhiwei <=
- [PATCH v3 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU, LIU Zhiwei, 2024/07/03
- [PATCH v3 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64, LIU Zhiwei, 2024/07/03
- [PATCH v3 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU, LIU Zhiwei, 2024/07/03
- [PATCH v3 6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU, LIU Zhiwei, 2024/07/03
- [PATCH v3 7/7] tests/avocado: Add an avocado test for riscv64, LIU Zhiwei, 2024/07/03