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[PATCH v3 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV6
From: |
LIU Zhiwei |
Subject: |
[PATCH v3 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64 |
Date: |
Wed, 3 Jul 2024 22:49:18 +0800 |
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure correct bit width based on sxl when running RV32 on RV64 QEMU.
This is required as MMU address translations run in S-mode.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu_helper.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 6709622dd3..fa3b845c85 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -887,12 +887,14 @@ static int get_physical_address(CPURISCVState *env,
hwaddr *physical,
CPUState *cs = env_cpu(env);
int va_bits = PGSHIFT + levels * ptidxbits + widened;
+ int sxlen = 16UL << riscv_cpu_sxl(env);
+ int sxlen_bytes = sxlen / 8;
if (first_stage == true) {
target_ulong mask, masked_msbs;
- if (TARGET_LONG_BITS > (va_bits - 1)) {
- mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
+ if (sxlen > (va_bits - 1)) {
+ mask = (1L << (sxlen - (va_bits - 1))) - 1;
} else {
mask = 0;
}
@@ -961,7 +963,7 @@ restart:
int pmp_prot;
int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr,
- sizeof(target_ulong),
+ sxlen_bytes,
MMU_DATA_LOAD, PRV_S);
if (pmp_ret != TRANSLATE_SUCCESS) {
return TRANSLATE_PMP_FAIL;
@@ -1113,7 +1115,7 @@ restart:
* it is no longer valid and we must re-walk the page table.
*/
MemoryRegion *mr;
- hwaddr l = sizeof(target_ulong), addr1;
+ hwaddr l = sxlen_bytes, addr1;
mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
false, MEMTXATTRS_UNSPECIFIED);
if (memory_region_is_ram(mr)) {
@@ -1125,7 +1127,12 @@ restart:
*/
*pte_pa = pte = updated_pte;
#else
- target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
+ target_ulong old_pte;
+ if (riscv_cpu_sxl(env) == MXL_RV32) {
+ old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, pte,
updated_pte);
+ } else {
+ old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
+ }
if (old_pte != pte) {
goto restart;
}
--
2.25.1
- [PATCH v3 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU, LIU Zhiwei, 2024/07/03
- [PATCH v3 1/7] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI, LIU Zhiwei, 2024/07/03
- [PATCH v3 2/7] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32, LIU Zhiwei, 2024/07/03
- [PATCH v3 3/7] target/riscv: Correct SXL return value for RV32 in RV64 QEMU, LIU Zhiwei, 2024/07/03
- [PATCH v3 4/7] target/riscv: Detect sxl to set bit width for RV32 in RV64,
LIU Zhiwei <=
- [PATCH v3 5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU, LIU Zhiwei, 2024/07/03
- [PATCH v3 6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU, LIU Zhiwei, 2024/07/03
- [PATCH v3 7/7] tests/avocado: Add an avocado test for riscv64, LIU Zhiwei, 2024/07/03