Re: [PATCH v3 6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU

[Alistair Francis]

On Thu, Jul 4, 2024 at 12:55 AM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>
> Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs
> in RV64 QEMU.
>
> Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  configs/targets/riscv64-softmmu.mak |  2 +-
>  target/riscv/cpu.c                  | 17 +++++++++++++----
>  2 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/configs/targets/riscv64-softmmu.mak 
> b/configs/targets/riscv64-softmmu.mak
> index 917980e63e..6c5de72e03 100644
> --- a/configs/targets/riscv64-softmmu.mak
> +++ b/configs/targets/riscv64-softmmu.mak
> @@ -2,6 +2,6 @@ TARGET_ARCH=riscv64
>  TARGET_BASE_ARCH=riscv
>  TARGET_SUPPORTS_MTTCG=y
>  TARGET_KVM_HAVE_GUEST_DEBUG=y
> -TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml 
> gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
> +TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml 
> gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml 
> gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-virtual.xml
>  # needed by boot.c
>  TARGET_NEED_FDT=y
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a2640cf259..fdd0f10aa5 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -630,8 +630,10 @@ static void rv64e_bare_cpu_init(Object *obj)
>      riscv_cpu_set_misa_ext(env, RVE);
>  }
>
> -#else /* !TARGET_RISCV64 */
> +#endif /* !TARGET_RISCV64 */
>
> +#if defined(TARGET_RISCV32) || \
> +    (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
>  static void rv32_base_cpu_init(Object *obj)
>  {
>      RISCVCPU *cpu = RISCV_CPU(obj);
> @@ -2944,6 +2946,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>  #if defined(TARGET_RISCV32)
>      DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY,       MXL_RV32,  
> riscv_any_cpu_init),
>      DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX,       MXL_RV32,  
> riscv_max_cpu_init),
> +#elif defined(TARGET_RISCV64)
> +    DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY,       MXL_RV64,  
> riscv_any_cpu_init),
> +    DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX,       MXL_RV64,  
> riscv_max_cpu_init),
> +#endif
> +
> +#if defined(TARGET_RISCV32) || \
> +    (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
>      DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32,    MXL_RV32,  
> rv32_base_cpu_init),
>      DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX,       MXL_RV32,  
> rv32_ibex_cpu_init),
>      DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32,  
> rv32_sifive_e_cpu_init),
> @@ -2951,9 +2960,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>      DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32,  
> rv32_sifive_u_cpu_init),
>      DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I,        MXL_RV32,  
> rv32i_bare_cpu_init),
>      DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E,        MXL_RV32,  
> rv32e_bare_cpu_init),
> -#elif defined(TARGET_RISCV64)
> -    DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY,       MXL_RV64,  
> riscv_any_cpu_init),
> -    DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX,       MXL_RV64,  
> riscv_max_cpu_init),
> +#endif
> +
> +#if defined(TARGET_RISCV64)
>      DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64,    MXL_RV64,  
> rv64_base_cpu_init),
>      DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64,  
> rv64_sifive_e_cpu_init),
>      DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64,  
> rv64_sifive_u_cpu_init),
> --
> 2.25.1
>
>