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[PULL 01/26] target/arm: Fix handling of LDAPR/STLR with negative offset
From: |
Peter Maydell |
Subject: |
[PULL 01/26] target/arm: Fix handling of LDAPR/STLR with negative offset |
Date: |
Thu, 18 Jul 2024 14:20:03 +0100 |
When we converted the LDAPR/STLR instructions to decodetree we
accidentally introduced a regression where the offset is negative.
The 9-bit immediate field is signed, and the old hand decoder
correctly used sextract32() to get it out of the insn word,
but the ldapr_stlr_i pattern in the decode file used "imm:9"
instead of "imm:s9", so it treated the field as unsigned.
Fix the pattern to treat the field as a signed immediate.
Cc: qemu-stable@nongnu.org
Fixes: 2521b6073b7 ("target/arm: Convert LDAPR/STLR (imm) to decodetree")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2419
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240709134504.3500007-2-peter.maydell@linaro.org
---
target/arm/tcg/a64.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 2922de700ca..62df4c4ceb4 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -520,7 +520,7 @@ LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5
LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=%ldra_imm
&ldapr_stlr_i rn rt imm sz sign ext
-@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i
+@ldapr_stlr_i .. ...... .. . imm:s9 .. rn:5 rt:5 &ldapr_stlr_i
STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0
ext=0
LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i sign=0
ext=0
LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign=1
ext=0 sz=0
--
2.34.1
- [PULL 17/26] hw/arm/smmu: Support nesting in the rest of commands, (continued)
- [PULL 17/26] hw/arm/smmu: Support nesting in the rest of commands, Peter Maydell, 2024/07/18
- [PULL 25/26] tests/arm-cpu-features: Do not assume PMU availability, Peter Maydell, 2024/07/18
- [PULL 04/26] hw/arm/smmu-common: Add missing size check for stage-1, Peter Maydell, 2024/07/18
- [PULL 06/26] hw/arm/smmuv3: Fix encoding of CLASS in events, Peter Maydell, 2024/07/18
- [PULL 11/26] hw/arm/smmuv3: Translate CD and TT using stage-2 table, Peter Maydell, 2024/07/18
- [PULL 07/26] hw/arm/smmu: Use enum for SMMU stage, Peter Maydell, 2024/07/18
- [PULL 21/26] hw/arm/smmu: Refactor SMMU OAS, Peter Maydell, 2024/07/18
- [PULL 01/26] target/arm: Fix handling of LDAPR/STLR with negative offset,
Peter Maydell <=
- [PULL 10/26] hw/arm/smmu: Introduce CACHED_ENTRY_TO_ADDR, Peter Maydell, 2024/07/18
- [PULL 09/26] hw/arm/smmu: Consolidate ASID and VMID types, Peter Maydell, 2024/07/18
- [PULL 19/26] hw/arm/smmuv3: Handle translation faults according to SMMUPTWEventInfo, Peter Maydell, 2024/07/18
- [PULL 22/26] target/arm: Use float_status copy in sme_fmopa_s, Peter Maydell, 2024/07/18
- [PULL 24/26] tests/tcg/aarch64: Add test cases for SME FMOPA (widening), Peter Maydell, 2024/07/18
- [PULL 08/26] hw/arm/smmu: Split smmuv3_translate(), Peter Maydell, 2024/07/18
- [PULL 15/26] hw/arm/smmu: Support nesting in smmuv3_range_inval(), Peter Maydell, 2024/07/18
- [PULL 18/26] hw/arm/smmuv3: Support nested SMMUs in smmuv3_notify_iova(), Peter Maydell, 2024/07/18
- [PULL 23/26] target/arm: Use FPST_F16 for SME FMOPA (widening), Peter Maydell, 2024/07/18
- [PULL 12/26] hw/arm/smmu-common: Rework TLB lookup for nesting, Peter Maydell, 2024/07/18