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[PULL 24/26] tests/tcg/aarch64: Add test cases for SME FMOPA (widening)
From: |
Peter Maydell |
Subject: |
[PULL 24/26] tests/tcg/aarch64: Add test cases for SME FMOPA (widening) |
Date: |
Thu, 18 Jul 2024 14:20:26 +0100 |
From: Daniyal Khan <danikhan632@gmail.com>
Signed-off-by: Daniyal Khan <danikhan632@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20240717060149.204788-4-richard.henderson@linaro.org
Message-Id: 172090222034.13953.16888708708822922098-1@git.sr.ht
[rth: Split test from a larger patch, tidy assembly]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/tcg/aarch64/sme-fmopa-1.c | 63 +++++++++++++++++++++++++++++++
tests/tcg/aarch64/sme-fmopa-2.c | 56 +++++++++++++++++++++++++++
tests/tcg/aarch64/sme-fmopa-3.c | 63 +++++++++++++++++++++++++++++++
tests/tcg/aarch64/Makefile.target | 5 ++-
4 files changed, 185 insertions(+), 2 deletions(-)
create mode 100644 tests/tcg/aarch64/sme-fmopa-1.c
create mode 100644 tests/tcg/aarch64/sme-fmopa-2.c
create mode 100644 tests/tcg/aarch64/sme-fmopa-3.c
diff --git a/tests/tcg/aarch64/sme-fmopa-1.c b/tests/tcg/aarch64/sme-fmopa-1.c
new file mode 100644
index 00000000000..652c4ea0902
--- /dev/null
+++ b/tests/tcg/aarch64/sme-fmopa-1.c
@@ -0,0 +1,63 @@
+/*
+ * SME outer product, 1 x 1.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <stdio.h>
+
+static void foo(float *dst)
+{
+ asm(".arch_extension sme\n\t"
+ "smstart\n\t"
+ "ptrue p0.s, vl4\n\t"
+ "fmov z0.s, #1.0\n\t"
+ /*
+ * An outer product of a vector of 1.0 by itself should be a matrix of
1.0.
+ * Note that we are using tile 1 here (za1.s) rather than tile 0.
+ */
+ "zero {za}\n\t"
+ "fmopa za1.s, p0/m, p0/m, z0.s, z0.s\n\t"
+ /*
+ * Read the first 4x4 sub-matrix of elements from tile 1:
+ * Note that za1h should be interchangeable here.
+ */
+ "mov w12, #0\n\t"
+ "mova z0.s, p0/m, za1v.s[w12, #0]\n\t"
+ "mova z1.s, p0/m, za1v.s[w12, #1]\n\t"
+ "mova z2.s, p0/m, za1v.s[w12, #2]\n\t"
+ "mova z3.s, p0/m, za1v.s[w12, #3]\n\t"
+ /*
+ * And store them to the input pointer (dst in the C code):
+ */
+ "st1w {z0.s}, p0, [%0]\n\t"
+ "add x0, x0, #16\n\t"
+ "st1w {z1.s}, p0, [x0]\n\t"
+ "add x0, x0, #16\n\t"
+ "st1w {z2.s}, p0, [x0]\n\t"
+ "add x0, x0, #16\n\t"
+ "st1w {z3.s}, p0, [x0]\n\t"
+ "smstop"
+ : : "r"(dst)
+ : "x12", "d0", "d1", "d2", "d3", "memory");
+}
+
+int main()
+{
+ float dst[16] = { };
+
+ foo(dst);
+
+ for (int i = 0; i < 16; i++) {
+ if (dst[i] != 1.0f) {
+ goto failure;
+ }
+ }
+ /* success */
+ return 0;
+
+ failure:
+ for (int i = 0; i < 16; i++) {
+ printf("%f%c", dst[i], i % 4 == 3 ? '\n' : ' ');
+ }
+ return 1;
+}
diff --git a/tests/tcg/aarch64/sme-fmopa-2.c b/tests/tcg/aarch64/sme-fmopa-2.c
new file mode 100644
index 00000000000..15f0972d835
--- /dev/null
+++ b/tests/tcg/aarch64/sme-fmopa-2.c
@@ -0,0 +1,56 @@
+/*
+ * SME outer product, FZ vs FZ16
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+
+static void test_fmopa(uint32_t *result)
+{
+ asm(".arch_extension sme\n\t"
+ "smstart\n\t" /* Z*, P* and ZArray cleared */
+ "ptrue p2.b, vl16\n\t" /* Limit vector length to 16 */
+ "ptrue p5.b, vl16\n\t"
+ "movi d0, #0x00ff\n\t" /* fp16 denormal */
+ "movi d16, #0x00ff\n\t"
+ "mov w15, #0x0001000000\n\t" /* FZ=1, FZ16=0 */
+ "msr fpcr, x15\n\t"
+ "fmopa za3.s, p2/m, p5/m, z16.h, z0.h\n\t"
+ "mov w15, #0\n\t"
+ "st1w {za3h.s[w15, 0]}, p2, [%0]\n\t"
+ "add %0, %0, #16\n\t"
+ "st1w {za3h.s[w15, 1]}, p2, [%0]\n\t"
+ "mov w15, #2\n\t"
+ "add %0, %0, #16\n\t"
+ "st1w {za3h.s[w15, 0]}, p2, [%0]\n\t"
+ "add %0, %0, #16\n\t"
+ "st1w {za3h.s[w15, 1]}, p2, [%0]\n\t"
+ "smstop"
+ : "+r"(result) :
+ : "x15", "x16", "p2", "p5", "d0", "d16", "memory");
+}
+
+int main(void)
+{
+ uint32_t result[4 * 4] = { };
+
+ test_fmopa(result);
+
+ if (result[0] != 0x2f7e0100) {
+ printf("Test failed: Incorrect output in first 4 bytes\n"
+ "Expected: %08x\n"
+ "Got: %08x\n",
+ 0x2f7e0100, result[0]);
+ return 1;
+ }
+
+ for (int i = 1; i < 16; ++i) {
+ if (result[i] != 0) {
+ printf("Test failed: Non-zero word at position %d\n", i);
+ return 1;
+ }
+ }
+
+ return 0;
+}
diff --git a/tests/tcg/aarch64/sme-fmopa-3.c b/tests/tcg/aarch64/sme-fmopa-3.c
new file mode 100644
index 00000000000..3bfec34914c
--- /dev/null
+++ b/tests/tcg/aarch64/sme-fmopa-3.c
@@ -0,0 +1,63 @@
+/*
+ * SME outer product, [ 1 2 3 4 ] squared
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <math.h>
+
+static const float i_1234[4] = {
+ 1.0f, 2.0f, 3.0f, 4.0f
+};
+
+static const float expected[4] = {
+ 4.515625f, 5.750000f, 6.984375f, 8.218750f
+};
+
+static void test_fmopa(float *result)
+{
+ asm(".arch_extension sme\n\t"
+ "smstart\n\t" /* ZArray cleared */
+ "ptrue p2.b, vl16\n\t" /* Limit vector length to 16 */
+ "ld1w {z0.s}, p2/z, [%1]\n\t"
+ "mov w15, #0\n\t"
+ "mov za3h.s[w15, 0], p2/m, z0.s\n\t"
+ "mov za3h.s[w15, 1], p2/m, z0.s\n\t"
+ "mov w15, #2\n\t"
+ "mov za3h.s[w15, 0], p2/m, z0.s\n\t"
+ "mov za3h.s[w15, 1], p2/m, z0.s\n\t"
+ "msr fpcr, xzr\n\t"
+ "fmopa za3.s, p2/m, p2/m, z0.h, z0.h\n\t"
+ "mov w15, #0\n\t"
+ "st1w {za3h.s[w15, 0]}, p2, [%0]\n"
+ "add %0, %0, #16\n\t"
+ "st1w {za3h.s[w15, 1]}, p2, [%0]\n\t"
+ "mov w15, #2\n\t"
+ "add %0, %0, #16\n\t"
+ "st1w {za3h.s[w15, 0]}, p2, [%0]\n\t"
+ "add %0, %0, #16\n\t"
+ "st1w {za3h.s[w15, 1]}, p2, [%0]\n\t"
+ "smstop"
+ : "+r"(result) : "r"(i_1234)
+ : "x15", "x16", "p2", "d0", "memory");
+}
+
+int main(void)
+{
+ float result[4 * 4] = { };
+ int ret = 0;
+
+ test_fmopa(result);
+
+ for (int i = 0; i < 4; i++) {
+ float actual = result[i];
+ if (fabsf(actual - expected[i]) > 0.001f) {
+ printf("Test failed at element %d: Expected %f, got %f\n",
+ i, expected[i], actual);
+ ret = 1;
+ }
+ }
+ return ret;
+}
diff --git a/tests/tcg/aarch64/Makefile.target
b/tests/tcg/aarch64/Makefile.target
index b53218e1156..8cc62eb4561 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -70,8 +70,9 @@ endif
# SME Tests
ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
-AARCH64_TESTS += sme-outprod1 sme-smopa-1 sme-smopa-2
-sme-outprod1 sme-smopa-1 sme-smopa-2: CFLAGS += $(CROSS_AS_HAS_ARMV9_SME)
+SME_TESTS = sme-outprod1 sme-smopa-1 sme-smopa-2 sme-fmopa-1 sme-fmopa-2
sme-fmopa-3
+AARCH64_TESTS += $(SME_TESTS)
+$(SME_TESTS): CFLAGS += $(CROSS_AS_HAS_ARMV9_SME)
endif
# System Registers Tests
--
2.34.1
- [PULL 04/26] hw/arm/smmu-common: Add missing size check for stage-1, (continued)
- [PULL 04/26] hw/arm/smmu-common: Add missing size check for stage-1, Peter Maydell, 2024/07/18
- [PULL 06/26] hw/arm/smmuv3: Fix encoding of CLASS in events, Peter Maydell, 2024/07/18
- [PULL 11/26] hw/arm/smmuv3: Translate CD and TT using stage-2 table, Peter Maydell, 2024/07/18
- [PULL 07/26] hw/arm/smmu: Use enum for SMMU stage, Peter Maydell, 2024/07/18
- [PULL 21/26] hw/arm/smmu: Refactor SMMU OAS, Peter Maydell, 2024/07/18
- [PULL 01/26] target/arm: Fix handling of LDAPR/STLR with negative offset, Peter Maydell, 2024/07/18
- [PULL 10/26] hw/arm/smmu: Introduce CACHED_ENTRY_TO_ADDR, Peter Maydell, 2024/07/18
- [PULL 09/26] hw/arm/smmu: Consolidate ASID and VMID types, Peter Maydell, 2024/07/18
- [PULL 19/26] hw/arm/smmuv3: Handle translation faults according to SMMUPTWEventInfo, Peter Maydell, 2024/07/18
- [PULL 22/26] target/arm: Use float_status copy in sme_fmopa_s, Peter Maydell, 2024/07/18
- [PULL 24/26] tests/tcg/aarch64: Add test cases for SME FMOPA (widening),
Peter Maydell <=
- [PULL 08/26] hw/arm/smmu: Split smmuv3_translate(), Peter Maydell, 2024/07/18
- [PULL 15/26] hw/arm/smmu: Support nesting in smmuv3_range_inval(), Peter Maydell, 2024/07/18
- [PULL 18/26] hw/arm/smmuv3: Support nested SMMUs in smmuv3_notify_iova(), Peter Maydell, 2024/07/18
- [PULL 23/26] target/arm: Use FPST_F16 for SME FMOPA (widening), Peter Maydell, 2024/07/18
- [PULL 12/26] hw/arm/smmu-common: Rework TLB lookup for nesting, Peter Maydell, 2024/07/18
- [PULL 13/26] hw/arm/smmu-common: Add support for nested TLB, Peter Maydell, 2024/07/18
- [PULL 20/26] hw/arm/smmuv3: Support and advertise nesting, Peter Maydell, 2024/07/18
- [PULL 16/26] hw/arm/smmu: Introduce smmu_iotlb_inv_asid_vmid, Peter Maydell, 2024/07/18
- [PULL 05/26] hw/arm/smmu: Fix IPA for stage-2 events, Peter Maydell, 2024/07/18
- [PULL 14/26] hw/arm/smmu-common: Support nested translation, Peter Maydell, 2024/07/18