[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 04/26] hw/arm/smmu-common: Add missing size check for stage-1
From: |
Peter Maydell |
Subject: |
[PULL 04/26] hw/arm/smmu-common: Add missing size check for stage-1 |
Date: |
Thu, 18 Jul 2024 14:20:06 +0100 |
From: Mostafa Saleh <smostafa@google.com>
According to the SMMU architecture specification (ARM IHI 0070 F.b),
in “3.4 Address sizes”
The address output from the translation causes a stage 1 Address Size
fault if it exceeds the range of the effective IPA size for the given CD.
However, this check was missing.
There is already a similar check for stage-2 against effective PA.
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
Message-id: 20240715084519.1189624-2-smostafa@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/smmu-common.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index b6601cc102e..e81b684d06c 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -381,6 +381,16 @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
goto error;
}
+ /*
+ * The address output from the translation causes a stage 1 Address
+ * Size fault if it exceeds the range of the effective IPA size for
+ * the given CD.
+ */
+ if (gpa >= (1ULL << cfg->oas)) {
+ info->type = SMMU_PTW_ERR_ADDR_SIZE;
+ goto error;
+ }
+
tlbe->entry.translated_addr = gpa;
tlbe->entry.iova = iova & ~mask;
tlbe->entry.addr_mask = mask;
--
2.34.1
- [PULL 00/26] target-arm queue, Peter Maydell, 2024/07/18
- [PULL 03/26] hw/display/bcm2835_fb: fix fb_use_offsets condition, Peter Maydell, 2024/07/18
- [PULL 02/26] target/arm: LDAPR should honour SCTLR_ELx.nAA, Peter Maydell, 2024/07/18
- [PULL 17/26] hw/arm/smmu: Support nesting in the rest of commands, Peter Maydell, 2024/07/18
- [PULL 25/26] tests/arm-cpu-features: Do not assume PMU availability, Peter Maydell, 2024/07/18
- [PULL 04/26] hw/arm/smmu-common: Add missing size check for stage-1,
Peter Maydell <=
- [PULL 06/26] hw/arm/smmuv3: Fix encoding of CLASS in events, Peter Maydell, 2024/07/18
- [PULL 11/26] hw/arm/smmuv3: Translate CD and TT using stage-2 table, Peter Maydell, 2024/07/18
- [PULL 07/26] hw/arm/smmu: Use enum for SMMU stage, Peter Maydell, 2024/07/18
- [PULL 21/26] hw/arm/smmu: Refactor SMMU OAS, Peter Maydell, 2024/07/18
- [PULL 01/26] target/arm: Fix handling of LDAPR/STLR with negative offset, Peter Maydell, 2024/07/18
- [PULL 10/26] hw/arm/smmu: Introduce CACHED_ENTRY_TO_ADDR, Peter Maydell, 2024/07/18
- [PULL 09/26] hw/arm/smmu: Consolidate ASID and VMID types, Peter Maydell, 2024/07/18