Re: [PATCH v2 01/13] target/riscv: Add properties for Indirect CSR Access extension

[Alistair Francis]

On Sat, Jul 27, 2024 at 11:33 AM Atish Kumar Patra <atishp@rivosinc.com> wrote:
>
> On Fri, Jul 26, 2024 at 12:42 AM Alistair Francis <alistair23@gmail.com> 
> wrote:
> >
> > On Wed, Jul 24, 2024 at 9:31 AM Atish Patra <atishp@rivosinc.com> wrote:
> > >
> > > From: Kaiwen Xue <kaiwenx@rivosinc.com>
> > >
> > > This adds the properties for sxcsrind. Definitions of new registers and
> > > implementations will come with future patches.
> > >
> > > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
> > > ---
> > >  target/riscv/cpu.c     | 2 ++
> > >  target/riscv/cpu_cfg.h | 2 ++
> > >  2 files changed, 4 insertions(+)
> > >
> > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > index a90808a3bace..ebc19090b40d 100644
> > > --- a/target/riscv/cpu.c
> > > +++ b/target/riscv/cpu.c
> > > @@ -183,12 +183,14 @@ const RISCVIsaExtData isa_edata_arr[] = {
> > >      ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
> > >      ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
> > >      ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
> > > +    ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_12_0, ext_smcsrind),
> >
> > This is actually part of the unpriv spec, so it's a bit weird that it
> > depends on the priv spec. But that's how it's all set up.
> >
>
> Smcsrind is part of priv spec[1]. Am I missing something ?
>
> https://drive.google.com/file/d/17GeetSnT5wW3xNuAHI95-SI1gPGd5sJ_/view

Ah, I just saw

"This specification has been merged into the Unprivileged Specification" at

https://github.com/riscvarchive/riscv-indirect-csr-access

Alistair

>
> > But shouldn't this be PRIV_VERSION_1_13_0?
> >
>
> Yes. Sorry I forgot about that. smcntrpmf should also be PRIV_VERSION_1_13_0.
> I will send a fix patch along with the v2 for assert fix.
>
> > Alistair