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Re: [PATCH v2 01/13] target/riscv: Add properties for Indirect CSR Acces
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From: |
Atish Kumar Patra |
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Subject: |
Re: [PATCH v2 01/13] target/riscv: Add properties for Indirect CSR Access extension |
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Date: |
Fri, 26 Jul 2024 18:33:24 -0700 |
On Fri, Jul 26, 2024 at 12:42 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Wed, Jul 24, 2024 at 9:31 AM Atish Patra <atishp@rivosinc.com> wrote:
> >
> > From: Kaiwen Xue <kaiwenx@rivosinc.com>
> >
> > This adds the properties for sxcsrind. Definitions of new registers and
> > implementations will come with future patches.
> >
> > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
> > ---
> > target/riscv/cpu.c | 2 ++
> > target/riscv/cpu_cfg.h | 2 ++
> > 2 files changed, 4 insertions(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index a90808a3bace..ebc19090b40d 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -183,12 +183,14 @@ const RISCVIsaExtData isa_edata_arr[] = {
> > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
> > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
> > ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
> > + ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_12_0, ext_smcsrind),
>
> This is actually part of the unpriv spec, so it's a bit weird that it
> depends on the priv spec. But that's how it's all set up.
>
Smcsrind is part of priv spec[1]. Am I missing something ?
https://drive.google.com/file/d/17GeetSnT5wW3xNuAHI95-SI1gPGd5sJ_/view
> But shouldn't this be PRIV_VERSION_1_13_0?
>
Yes. Sorry I forgot about that. smcntrpmf should also be PRIV_VERSION_1_13_0.
I will send a fix patch along with the v2 for assert fix.
> Alistair
- [PATCH v2 00/13] Add RISC-V Counter delegation ISA extension support, Atish Patra, 2024/07/23
- [PATCH v2 04/13] target/riscv: Support generic CSR indirect access, Atish Patra, 2024/07/23
- [PATCH v2 03/13] target/riscv: Enable S*stateen bits for AIA, Atish Patra, 2024/07/23
- [PATCH v2 02/13] target/riscv: Decouple AIA processing from xiselect and xireg, Atish Patra, 2024/07/23
- [PATCH v2 05/13] target/riscv: Add counter delegation definitions, Atish Patra, 2024/07/23
- [PATCH v2 07/13] target/riscv: Add counter delegation/configuration support, Atish Patra, 2024/07/23
- [PATCH v2 13/13] target/riscv: Enable PMU related extensions to preferred rule, Atish Patra, 2024/07/23
- [PATCH v2 10/13] target/riscv: Enable sscofpmf for bare cpu by default, Atish Patra, 2024/07/23
- [PATCH v2 12/13] target/riscv: Add a preferred ISA extension rule, Atish Patra, 2024/07/23
- [PATCH v2 09/13] target/riscv: Invoke pmu init after feature enable, Atish Patra, 2024/07/23