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[PULL 49/96] pnv/xive2: Fail VST entry address computation if table has
From: |
Nicholas Piggin |
Subject: |
[PULL 49/96] pnv/xive2: Fail VST entry address computation if table has no VSD |
Date: |
Fri, 26 Jul 2024 09:53:22 +1000 |
From: Frederic Barrat <fbarrat@linux.ibm.com>
Fail VST entry address computation if firmware doesn't define a descriptor
for one of the Virtualization Structure Tables (VST), there's no point in
trying to compute the address of its entry. Abort the operation and log
an error.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/intc/pnv_xive2.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 08b9166a09..9fbd44f974 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -244,6 +244,11 @@ static uint64_t pnv_xive2_vst_addr(PnvXive2 *xive,
uint32_t type, uint8_t blk,
}
vsd = xive->vsds[type][blk];
+ if (vsd == 0) {
+ xive2_error(xive, "VST: vsd == 0 block id %d for VST %s %d !?",
+ blk, info->name, idx);
+ return 0;
+ }
/* Remote VST access */
if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) {
--
2.45.2
- [PULL 39/96] hw/block: Add Microchip's 25CSM04 to m25p80, (continued)
- [PULL 39/96] hw/block: Add Microchip's 25CSM04 to m25p80, Nicholas Piggin, 2024/07/25
- [PULL 40/96] hw/ppc: SPI controller wiring to P10 chip, Nicholas Piggin, 2024/07/25
- [PULL 41/96] tests/qtest: Add pnv-spi-seeprom qtest, Nicholas Piggin, 2024/07/25
- [PULL 42/96] pnv/xive2: XIVE2 Cache Watch, Cache Flush and Sync Injection support, Nicholas Piggin, 2024/07/25
- [PULL 44/96] pnv/xive: Support cache flush and queue sync inject with notifications, Nicholas Piggin, 2024/07/25
- [PULL 46/96] pnv/xive2: Configure Virtualization Structure Tables through the PC, Nicholas Piggin, 2024/07/25
- [PULL 45/96] pnv/xive2: Add NVG and NVC to cache watch facility, Nicholas Piggin, 2024/07/25
- [PULL 43/96] pnv/xive2: Structure/define alignment changes, Nicholas Piggin, 2024/07/25
- [PULL 47/96] pnv/xive2: Enable VST NVG and NVC index compression, Nicholas Piggin, 2024/07/25
- [PULL 48/96] pnv/xive2: Set Translation Table for the NVC port space, Nicholas Piggin, 2024/07/25
- [PULL 49/96] pnv/xive2: Fail VST entry address computation if table has no VSD,
Nicholas Piggin <=
- [PULL 51/96] pnv/xive2: Refine TIMA 'info pic' output, Nicholas Piggin, 2024/07/25
- [PULL 50/96] pnv/xive2: Move xive2_nvp_pic_print_info() to xive2.c, Nicholas Piggin, 2024/07/25
- [PULL 52/96] pnv/xive2: Dump more END state with 'info pic', Nicholas Piggin, 2024/07/25
- [PULL 53/96] target/ppc: Move VMX integer add/sub saturate insns to decodetree., Nicholas Piggin, 2024/07/25
- [PULL 54/96] target/ppc: Improve VMX integer add/sub saturate instructions., Nicholas Piggin, 2024/07/25
- [PULL 55/96] target/ppc: Move ISA300 flag check out of do_helper_XX3., Nicholas Piggin, 2024/07/25
- [PULL 56/96] target/ppc: Move VSX arithmetic and max/min insns to decodetree., Nicholas Piggin, 2024/07/25
- [PULL 57/96] target/ppc: Move VSX logical instructions to decodetree., Nicholas Piggin, 2024/07/25
- [PULL 58/96] target/ppc: Moving VSX scalar storage access insns to decodetree., Nicholas Piggin, 2024/07/25
- [PULL 59/96] target/ppc: Move VSX vector with length storage access insns to decodetree., Nicholas Piggin, 2024/07/25