[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 51/96] pnv/xive2: Refine TIMA 'info pic' output
From: |
Nicholas Piggin |
Subject: |
[PULL 51/96] pnv/xive2: Refine TIMA 'info pic' output |
Date: |
Fri, 26 Jul 2024 09:53:24 +1000 |
From: Frederic Barrat <fbarrat@linux.ibm.com>
In XIVE Gen 2 there were some minor changes to the TIMA header that were
updated when printed.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/intc/xive.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 70f11f993b..5a02dd8e02 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -692,9 +692,15 @@ void xive_tctx_pic_print_info(XiveTCTX *tctx, GString *buf)
}
}
- g_string_append_printf(buf, "CPU[%04x]: "
- "QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR W2\n",
- cpu_index);
+ if (xive_presenter_get_config(tctx->xptr) & XIVE_PRESENTER_GEN1_TIMA_OS) {
+ g_string_append_printf(buf, "CPU[%04x]: "
+ "QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR"
+ " W2\n", cpu_index);
+ } else {
+ g_string_append_printf(buf, "CPU[%04x]: "
+ "QW NSR CPPR IPB LSMFB - LGS T PIPR"
+ " W2\n", cpu_index);
+ }
for (i = 0; i < XIVE_TM_RING_COUNT; i++) {
char *s = xive_tctx_ring_print(&tctx->regs[i * XIVE_TM_RING_SIZE]);
--
2.45.2
- [PULL 40/96] hw/ppc: SPI controller wiring to P10 chip, (continued)
- [PULL 40/96] hw/ppc: SPI controller wiring to P10 chip, Nicholas Piggin, 2024/07/25
- [PULL 41/96] tests/qtest: Add pnv-spi-seeprom qtest, Nicholas Piggin, 2024/07/25
- [PULL 42/96] pnv/xive2: XIVE2 Cache Watch, Cache Flush and Sync Injection support, Nicholas Piggin, 2024/07/25
- [PULL 44/96] pnv/xive: Support cache flush and queue sync inject with notifications, Nicholas Piggin, 2024/07/25
- [PULL 46/96] pnv/xive2: Configure Virtualization Structure Tables through the PC, Nicholas Piggin, 2024/07/25
- [PULL 45/96] pnv/xive2: Add NVG and NVC to cache watch facility, Nicholas Piggin, 2024/07/25
- [PULL 43/96] pnv/xive2: Structure/define alignment changes, Nicholas Piggin, 2024/07/25
- [PULL 47/96] pnv/xive2: Enable VST NVG and NVC index compression, Nicholas Piggin, 2024/07/25
- [PULL 48/96] pnv/xive2: Set Translation Table for the NVC port space, Nicholas Piggin, 2024/07/25
- [PULL 49/96] pnv/xive2: Fail VST entry address computation if table has no VSD, Nicholas Piggin, 2024/07/25
- [PULL 51/96] pnv/xive2: Refine TIMA 'info pic' output,
Nicholas Piggin <=
- [PULL 50/96] pnv/xive2: Move xive2_nvp_pic_print_info() to xive2.c, Nicholas Piggin, 2024/07/25
- [PULL 52/96] pnv/xive2: Dump more END state with 'info pic', Nicholas Piggin, 2024/07/25
- [PULL 53/96] target/ppc: Move VMX integer add/sub saturate insns to decodetree., Nicholas Piggin, 2024/07/25
- [PULL 54/96] target/ppc: Improve VMX integer add/sub saturate instructions., Nicholas Piggin, 2024/07/25
- [PULL 55/96] target/ppc: Move ISA300 flag check out of do_helper_XX3., Nicholas Piggin, 2024/07/25
- [PULL 56/96] target/ppc: Move VSX arithmetic and max/min insns to decodetree., Nicholas Piggin, 2024/07/25
- [PULL 57/96] target/ppc: Move VSX logical instructions to decodetree., Nicholas Piggin, 2024/07/25
- [PULL 58/96] target/ppc: Moving VSX scalar storage access insns to decodetree., Nicholas Piggin, 2024/07/25
- [PULL 59/96] target/ppc: Move VSX vector with length storage access insns to decodetree., Nicholas Piggin, 2024/07/25
- [PULL 60/96] target/ppc: Move VSX vector storage access insns to decodetree., Nicholas Piggin, 2024/07/25