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[PULL 29/39] target/riscv: Add svukte extension capability variable
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From: |
Alistair Francis |
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Subject: |
[PULL 29/39] target/riscv: Add svukte extension capability variable |
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Date: |
Thu, 19 Dec 2024 08:29:59 +1000 |
From: "Fea.Wang" <fea.wang@sifive.com>
Refer to the draft of svukte extension from:
https://github.com/riscv/riscv-isa-manual/pull/1564
Svukte provides a means to make user-mode accesses to supervisor memory
raise page faults in constant time, mitigating attacks that attempt to
discover the supervisor software's address-space layout.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-2-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 59d6fc445d..d8771ca641 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -84,6 +84,7 @@ struct RISCVCPUConfig {
bool ext_svnapot;
bool ext_svpbmt;
bool ext_svvptc;
+ bool ext_svukte;
bool ext_zdinx;
bool ext_zaamo;
bool ext_zacas;
--
2.47.1
- [PULL 26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system., (continued)
- [PULL 26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system., Alistair Francis, 2024/12/18
- [PULL 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU, Alistair Francis, 2024/12/18
- [PULL 27/39] hw/riscv: Add a new struct RISCVBootInfo, Alistair Francis, 2024/12/18
- [PULL 20/39] qtest: allow SPCR acpi table changes, Alistair Francis, 2024/12/18
- [PULL 28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd, Alistair Francis, 2024/12/18
- [PULL 31/39] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/18
- [PULL 33/39] target/riscv: Expose svukte ISA extension, Alistair Francis, 2024/12/18
- [PULL 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver, Alistair Francis, 2024/12/18
- [PULL 17/39] target/riscv/kvm: remove irqchip_split() restriction, Alistair Francis, 2024/12/18
- [PULL 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses, Alistair Francis, 2024/12/18
- [PULL 29/39] target/riscv: Add svukte extension capability variable,
Alistair Francis <=
- [PULL 35/39] target/riscv: Include missing headers in 'vector_internals.h', Alistair Francis, 2024/12/18
- [PULL 34/39] target/riscv: Check svukte is not enabled in RV32, Alistair Francis, 2024/12/18
- [PULL 23/39] MAINTAINERS: Cover RISC-V HTIF interface, Alistair Francis, 2024/12/18
- [PULL 30/39] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/18
- [PULL 38/39] target/riscv: add ssstateen, Alistair Francis, 2024/12/18
- [PULL 18/39] docs: update riscv/virt.rst with kernel-irqchip=split support, Alistair Francis, 2024/12/18
- [PULL 36/39] target/riscv: Include missing headers in 'internals.h', Alistair Francis, 2024/12/18
- Re: [PULL 00/39] riscv-to-apply queue, Stefan Hajnoczi, 2024/12/19