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[PULL 34/39] target/riscv: Check svukte is not enabled in RV32
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From: |
Alistair Francis |
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Subject: |
[PULL 34/39] target/riscv: Check svukte is not enabled in RV32 |
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Date: |
Thu, 19 Dec 2024 08:30:04 +1000 |
From: "Fea.Wang" <fea.wang@sifive.com>
The spec explicitly says svukte doesn't support RV32. So check that it
is not enabled in RV32.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-7-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/tcg/tcg-cpu.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index c62c221696..3b99c8c9e3 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -652,6 +652,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
Error **errp)
return;
}
+ if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) {
+ error_setg(errp, "svukte is not supported for RV32");
+ return;
+ }
+
/*
* Disable isa extensions based on priv spec after we
* validated and set everything we need.
--
2.47.1
- [PULL 27/39] hw/riscv: Add a new struct RISCVBootInfo, (continued)
- [PULL 27/39] hw/riscv: Add a new struct RISCVBootInfo, Alistair Francis, 2024/12/18
- [PULL 20/39] qtest: allow SPCR acpi table changes, Alistair Francis, 2024/12/18
- [PULL 28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd, Alistair Francis, 2024/12/18
- [PULL 31/39] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/18
- [PULL 33/39] target/riscv: Expose svukte ISA extension, Alistair Francis, 2024/12/18
- [PULL 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver, Alistair Francis, 2024/12/18
- [PULL 17/39] target/riscv/kvm: remove irqchip_split() restriction, Alistair Francis, 2024/12/18
- [PULL 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses, Alistair Francis, 2024/12/18
- [PULL 29/39] target/riscv: Add svukte extension capability variable, Alistair Francis, 2024/12/18
- [PULL 35/39] target/riscv: Include missing headers in 'vector_internals.h', Alistair Francis, 2024/12/18
- [PULL 34/39] target/riscv: Check svukte is not enabled in RV32,
Alistair Francis <=
- [PULL 23/39] MAINTAINERS: Cover RISC-V HTIF interface, Alistair Francis, 2024/12/18
- [PULL 30/39] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/18
- [PULL 38/39] target/riscv: add ssstateen, Alistair Francis, 2024/12/18
- [PULL 18/39] docs: update riscv/virt.rst with kernel-irqchip=split support, Alistair Francis, 2024/12/18
- [PULL 36/39] target/riscv: Include missing headers in 'internals.h', Alistair Francis, 2024/12/18
- Re: [PULL 00/39] riscv-to-apply queue, Stefan Hajnoczi, 2024/12/19