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[PULL 36/39] target/riscv: Include missing headers in 'internals.h'
From: |
Alistair Francis |
Subject: |
[PULL 36/39] target/riscv: Include missing headers in 'internals.h' |
Date: |
Thu, 19 Dec 2024 08:30:06 +1000 |
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Rather than relying on implicit includes, explicit them,
in order to avoid when refactoring unrelated headers:
target/riscv/internals.h:49:15: error: use of undeclared identifier 'PRV_S'
49 | ret = PRV_S;
| ^
target/riscv/internals.h:93:9: error: call to undeclared function
'env_archcpu'; ISO C99 and later do not support implicit function declarations
[-Wimplicit-function-declaration]
93 | if (env_archcpu(env)->cfg.ext_zfinx) {
| ^
target/riscv/internals.h:101:15: error: unknown type name 'float32'; did you
mean 'float'?
101 | static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f)
| ^~~~~~~
| float
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241203200828.47311-3-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/internals.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index ddbdee885b..76934eaa7b 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -19,7 +19,10 @@
#ifndef RISCV_CPU_INTERNALS_H
#define RISCV_CPU_INTERNALS_H
+#include "exec/cpu-common.h"
#include "hw/registerfields.h"
+#include "fpu/softfloat-types.h"
+#include "target/riscv/cpu_bits.h"
/*
* The current MMU Modes are:
--
2.47.1
- [PULL 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver, (continued)
- [PULL 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver, Alistair Francis, 2024/12/18
- [PULL 17/39] target/riscv/kvm: remove irqchip_split() restriction, Alistair Francis, 2024/12/18
- [PULL 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses, Alistair Francis, 2024/12/18
- [PULL 29/39] target/riscv: Add svukte extension capability variable, Alistair Francis, 2024/12/18
- [PULL 35/39] target/riscv: Include missing headers in 'vector_internals.h', Alistair Francis, 2024/12/18
- [PULL 34/39] target/riscv: Check svukte is not enabled in RV32, Alistair Francis, 2024/12/18
- [PULL 23/39] MAINTAINERS: Cover RISC-V HTIF interface, Alistair Francis, 2024/12/18
- [PULL 30/39] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/18
- [PULL 38/39] target/riscv: add ssstateen, Alistair Francis, 2024/12/18
- [PULL 18/39] docs: update riscv/virt.rst with kernel-irqchip=split support, Alistair Francis, 2024/12/18
- [PULL 36/39] target/riscv: Include missing headers in 'internals.h',
Alistair Francis <=
- Re: [PULL 00/39] riscv-to-apply queue, Stefan Hajnoczi, 2024/12/19