[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v2 35/39] target/riscv: Include missing headers in 'vector_interna
|
From: |
Alistair Francis |
|
Subject: |
[PULL v2 35/39] target/riscv: Include missing headers in 'vector_internals.h' |
|
Date: |
Fri, 20 Dec 2024 11:54:35 +1000 |
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Rather than relying on implicit includes, explicit them,
in order to avoid when refactoring unrelated headers:
target/riscv/vector_internals.h:36:12: error: call to undeclared function
'FIELD_EX32'; ISO C99 and later do not support implicit function declarations
[-Wimplicit-function-declaration]
36 | return FIELD_EX32(simd_data(desc), VDATA, NF);
| ^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241203200828.47311-2-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_internals.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
index 9e1e15b575..a11cc8366d 100644
--- a/target/riscv/vector_internals.h
+++ b/target/riscv/vector_internals.h
@@ -20,6 +20,7 @@
#define TARGET_RISCV_VECTOR_INTERNALS_H
#include "qemu/bitops.h"
+#include "hw/registerfields.h"
#include "cpu.h"
#include "tcg/tcg-gvec-desc.h"
#include "internals.h"
--
2.47.1
- [PULL v2 23/39] MAINTAINERS: Cover RISC-V HTIF interface, (continued)
- [PULL v2 23/39] MAINTAINERS: Cover RISC-V HTIF interface, Alistair Francis, 2024/12/19
- [PULL v2 30/39] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/19
- [PULL v2 28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd, Alistair Francis, 2024/12/19
- [PULL v2 26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system., Alistair Francis, 2024/12/19
- [PULL v2 27/39] hw/riscv: Add a new struct RISCVBootInfo, Alistair Francis, 2024/12/19
- [PULL v2 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses, Alistair Francis, 2024/12/19
- [PULL v2 31/39] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/19
- [PULL v2 32/39] target/riscv: Check memory access to meet svukte rule, Alistair Francis, 2024/12/19
- [PULL v2 34/39] target/riscv: Check svukte is not enabled in RV32, Alistair Francis, 2024/12/19
- [PULL v2 33/39] target/riscv: Expose svukte ISA extension, Alistair Francis, 2024/12/19
- [PULL v2 35/39] target/riscv: Include missing headers in 'vector_internals.h',
Alistair Francis <=
- [PULL v2 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver, Alistair Francis, 2024/12/19
- [PULL v2 36/39] target/riscv: Include missing headers in 'internals.h', Alistair Francis, 2024/12/19
- [PULL v2 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU, Alistair Francis, 2024/12/19
- [PULL v2 38/39] target/riscv: add ssstateen, Alistair Francis, 2024/12/19
- Re: [PULL v2 00/39] riscv-to-apply queue, Stefan Hajnoczi, 2024/12/21