Re: [PULL v2 00/39] riscv-to-apply queue

qemu-devel

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any 
user-visible changes.

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[PULL v2 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses, (continued)
- [PULL v2 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses, Alistair Francis, 2024/12/19
- [PULL v2 31/39] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/19
- [PULL v2 32/39] target/riscv: Check memory access to meet svukte rule, Alistair Francis, 2024/12/19
- [PULL v2 34/39] target/riscv: Check svukte is not enabled in RV32, Alistair Francis, 2024/12/19
- [PULL v2 33/39] target/riscv: Expose svukte ISA extension, Alistair Francis, 2024/12/19
- [PULL v2 35/39] target/riscv: Include missing headers in 'vector_internals.h', Alistair Francis, 2024/12/19
- [PULL v2 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver, Alistair Francis, 2024/12/19
- [PULL v2 36/39] target/riscv: Include missing headers in 'internals.h', Alistair Francis, 2024/12/19
- [PULL v2 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU, Alistair Francis, 2024/12/19
- [PULL v2 38/39] target/riscv: add ssstateen, Alistair Francis, 2024/12/19
- Re: [PULL v2 00/39] riscv-to-apply queue, Stefan Hajnoczi <=