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[PULL v2 36/39] target/riscv: Include missing headers in 'internals.h'
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From: |
Alistair Francis |
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Subject: |
[PULL v2 36/39] target/riscv: Include missing headers in 'internals.h' |
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Date: |
Fri, 20 Dec 2024 11:54:36 +1000 |
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Rather than relying on implicit includes, explicit them,
in order to avoid when refactoring unrelated headers:
target/riscv/internals.h:49:15: error: use of undeclared identifier 'PRV_S'
49 | ret = PRV_S;
| ^
target/riscv/internals.h:93:9: error: call to undeclared function
'env_archcpu'; ISO C99 and later do not support implicit function declarations
[-Wimplicit-function-declaration]
93 | if (env_archcpu(env)->cfg.ext_zfinx) {
| ^
target/riscv/internals.h:101:15: error: unknown type name 'float32'; did you
mean 'float'?
101 | static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f)
| ^~~~~~~
| float
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241203200828.47311-3-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/internals.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index ddbdee885b..76934eaa7b 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -19,7 +19,10 @@
#ifndef RISCV_CPU_INTERNALS_H
#define RISCV_CPU_INTERNALS_H
+#include "exec/cpu-common.h"
#include "hw/registerfields.h"
+#include "fpu/softfloat-types.h"
+#include "target/riscv/cpu_bits.h"
/*
* The current MMU Modes are:
--
2.47.1
- [PULL v2 28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd, (continued)
- [PULL v2 28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd, Alistair Francis, 2024/12/19
- [PULL v2 26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system., Alistair Francis, 2024/12/19
- [PULL v2 27/39] hw/riscv: Add a new struct RISCVBootInfo, Alistair Francis, 2024/12/19
- [PULL v2 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses, Alistair Francis, 2024/12/19
- [PULL v2 31/39] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/19
- [PULL v2 32/39] target/riscv: Check memory access to meet svukte rule, Alistair Francis, 2024/12/19
- [PULL v2 34/39] target/riscv: Check svukte is not enabled in RV32, Alistair Francis, 2024/12/19
- [PULL v2 33/39] target/riscv: Expose svukte ISA extension, Alistair Francis, 2024/12/19
- [PULL v2 35/39] target/riscv: Include missing headers in 'vector_internals.h', Alistair Francis, 2024/12/19
- [PULL v2 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver, Alistair Francis, 2024/12/19
- [PULL v2 36/39] target/riscv: Include missing headers in 'internals.h',
Alistair Francis <=
- [PULL v2 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU, Alistair Francis, 2024/12/19
- [PULL v2 38/39] target/riscv: add ssstateen, Alistair Francis, 2024/12/19
- Re: [PULL v2 00/39] riscv-to-apply queue, Stefan Hajnoczi, 2024/12/21