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[PULL 54/67] ppc/xive2: Allow 1-byte write of Target field in TIMA
From: |
Nicholas Piggin |
Subject: |
[PULL 54/67] ppc/xive2: Allow 1-byte write of Target field in TIMA |
Date: |
Mon, 4 Nov 2024 10:18:43 +1000 |
From: Glenn Miles <milesg@linux.vnet.ibm.com>
When running PowerVM, the console is littered with XIVE traces regarding
invalid writes to TIMA address 0x100b6 due to a lack of support for writes
to the "TARGET" field which was added for XIVE GEN2. To fix this, we add
special op support for 1-byte writes to this field.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/intc/xive.c | 2 ++
hw/intc/xive2.c | 13 +++++++++++++
include/hw/ppc/xive2.h | 2 ++
include/hw/ppc/xive_regs.h | 1 +
4 files changed, 18 insertions(+)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index caa8dc74b6..574ac685c3 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -546,6 +546,8 @@ static const XiveTmOp xive2_tm_operations[] = {
NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL,
xive_tm_vt_poll },
+ { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_T, 1, xive2_tm_set_hv_target,
+ NULL },
/* MMIOs above 2K : special operations with side effects */
{ XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL,
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 26b6e72129..8d3d69a0db 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -585,6 +585,19 @@ void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX
*tctx,
}
}
+static void xive2_tctx_set_target(XiveTCTX *tctx, uint8_t ring, uint8_t target)
+{
+ uint8_t *regs = &tctx->regs[ring];
+
+ regs[TM_T] = target;
+}
+
+void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
+{
+ xive2_tctx_set_target(tctx, TM_QW3_HV_PHYS, value & 0xff);
+}
+
/*
* XIVE Router (aka. Virtualization Controller or IVRE)
*/
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index b7a7c33ddd..36bd0e747f 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -121,5 +121,7 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX
*tctx,
hwaddr offset, unsigned size);
void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, uint64_t value, unsigned size);
+void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size);
#endif /* PPC_XIVE2_H */
diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h
index 27a744d50d..f8f05deafd 100644
--- a/include/hw/ppc/xive_regs.h
+++ b/include/hw/ppc/xive_regs.h
@@ -79,6 +79,7 @@
#define TM_INC 0x5 /* - + - + */
#define TM_LGS 0x5 /* + + + + */ /* Rename P10 */
#define TM_AGE 0x6 /* - + - + */
+#define TM_T 0x6 /* - + - + */ /* Rename P10 */
#define TM_PIPR 0x7 /* - + - + */
#define TM_OGEN 0xF /* - + - - */ /* P10 only */
--
2.45.2
- [PULL 45/67] spapr: nested: Add Power11 capability support for Nested PAPR guests in TCG L0, (continued)
- [PULL 45/67] spapr: nested: Add Power11 capability support for Nested PAPR guests in TCG L0, Nicholas Piggin, 2024/11/03
- [PULL 41/67] target/ppc: simplify var usage in ppc_next_unmasked_interrupt, Nicholas Piggin, 2024/11/03
- [PULL 48/67] pnv/xive: TIMA patch sets pre-req alignment and formatting changes, Nicholas Piggin, 2024/11/03
- [PULL 47/67] ppc/xive: Fix ESB length overflow on 32-bit hosts, Nicholas Piggin, 2024/11/03
- [PULL 49/67] pnv/xive2: Define OGEN field in the TIMA, Nicholas Piggin, 2024/11/03
- [PULL 51/67] pnv/xive2: Support for "OS LGS Push" TIMA operation, Nicholas Piggin, 2024/11/03
- [PULL 50/67] ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line", Nicholas Piggin, 2024/11/03
- [PULL 52/67] ppc/xive2: Dump more NVP state with 'info pic', Nicholas Piggin, 2024/11/03
- [PULL 57/67] ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line", Nicholas Piggin, 2024/11/03
- [PULL 44/67] spapr: nested: Add support for DPDES SPR in GSB for TCG L0, Nicholas Piggin, 2024/11/03
- [PULL 54/67] ppc/xive2: Allow 1-byte write of Target field in TIMA,
Nicholas Piggin <=
- [PULL 59/67] pnv/xive: Update PIPR when updating CPPR, Nicholas Piggin, 2024/11/03
- [PULL 60/67] pnv/xive2: TIMA support for 8-byte OS context push for PHYP, Nicholas Piggin, 2024/11/03
- [PULL 61/67] pnv/xive2: TIMA CI ops using alternative offsets or byte lengths, Nicholas Piggin, 2024/11/03
- [PULL 53/67] ppc/xive2: Dump the VP-group and crowd tables with 'info pic', Nicholas Piggin, 2024/11/03
- [PULL 55/67] ppc/xive2: Support "Pull Thread Context to Register" operation, Nicholas Piggin, 2024/11/03
- [PULL 58/67] pnv/xive: Add special handling for pool targets, Nicholas Piggin, 2024/11/03
- [PULL 56/67] ppc/xive2: Change context/ring specific functions to be generic, Nicholas Piggin, 2024/11/03
- [PULL 62/67] tests/qtest: Add XIVE tests for the powernv10 machine, Nicholas Piggin, 2024/11/03
- [PULL 63/67] hw/ppc: Consolidate e500 initial mapping creation functions, Nicholas Piggin, 2024/11/03
- [PULL 64/67] hw/ppc: Consolidate ppc440 initial mapping creation functions, Nicholas Piggin, 2024/11/03