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[PULL 45/67] spapr: nested: Add Power11 capability support for Nested PA
From: |
Nicholas Piggin |
Subject: |
[PULL 45/67] spapr: nested: Add Power11 capability support for Nested PAPR guests in TCG L0 |
Date: |
Mon, 4 Nov 2024 10:18:34 +1000 |
From: Amit Machhiwal <amachhiw@linux.ibm.com>
The Power11 architected and raw mode support in Linux was merged via [1]
and the corresponding support in QEMU is waiting to be added by [2]
which in V6 currently.
Add the Power11 capabilities and the required handling in TCG L0
implementation of the "Nested PAPR API".
Note: This patch is based on [2].
[1] https://lore.kernel.org/all/20240221044623.1598642-1-mpe@ellerman.id.au/
[2] https://lore.kernel.org/all/20240731055022.696051-1-adityag@linux.ibm.com/
Signed-off-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr_nested.c | 12 +++++++++++-
include/hw/ppc/spapr_nested.h | 5 ++++-
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c
index 1b41c8fb8b..7def8eb73b 100644
--- a/hw/ppc/spapr_nested.c
+++ b/hw/ppc/spapr_nested.c
@@ -771,6 +771,7 @@ static void copy_logical_pvr(void *a, void *b, bool set)
if (*pvr_logical_ptr) {
switch (*pvr_logical_ptr) {
+ case CPU_POWERPC_LOGICAL_3_10_P11:
case CPU_POWERPC_LOGICAL_3_10:
pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00;
break;
@@ -1185,6 +1186,12 @@ static target_ulong h_guest_get_capabilities(PowerPCCPU
*cpu,
return H_PARAMETER;
}
+ /* P11 capabilities */
+ if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10_P11, 0,
+ spapr->max_compat_pvr)) {
+ env->gpr[4] |= H_GUEST_CAPABILITIES_P11_MODE;
+ }
+
/* P10 capabilities */
if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0,
spapr->max_compat_pvr)) {
@@ -1227,7 +1234,10 @@ static target_ulong h_guest_set_capabilities(PowerPCCPU
*cpu,
env->gpr[4] = 1;
/* set R5 to the first supported Power Processor Mode */
- if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0,
+ if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10_P11, 0,
+ spapr->max_compat_pvr)) {
+ env->gpr[5] = H_GUEST_CAP_P11_MODE_BMAP;
+ } else if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0,
spapr->max_compat_pvr)) {
env->gpr[5] = H_GUEST_CAP_P10_MODE_BMAP;
} else if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0,
diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h
index 3b5cd993c2..e420220484 100644
--- a/include/hw/ppc/spapr_nested.h
+++ b/include/hw/ppc/spapr_nested.h
@@ -211,11 +211,14 @@ typedef struct SpaprMachineStateNestedGuest {
#define H_GUEST_CAPABILITIES_COPY_MEM 0x8000000000000000
#define H_GUEST_CAPABILITIES_P9_MODE 0x4000000000000000
#define H_GUEST_CAPABILITIES_P10_MODE 0x2000000000000000
-#define H_GUEST_CAP_VALID_MASK (H_GUEST_CAPABILITIES_P10_MODE | \
+#define H_GUEST_CAPABILITIES_P11_MODE 0x1000000000000000
+#define H_GUEST_CAP_VALID_MASK (H_GUEST_CAPABILITIES_P11_MODE | \
+ H_GUEST_CAPABILITIES_P10_MODE | \
H_GUEST_CAPABILITIES_P9_MODE)
#define H_GUEST_CAP_COPY_MEM_BMAP 0
#define H_GUEST_CAP_P9_MODE_BMAP 1
#define H_GUEST_CAP_P10_MODE_BMAP 2
+#define H_GUEST_CAP_P11_MODE_BMAP 3
#define PAPR_NESTED_GUEST_MAX 4096
#define H_GUEST_DELETE_ALL_FLAG 0x8000000000000000ULL
#define PAPR_NESTED_GUEST_VCPU_MAX 2048
--
2.45.2
- [PULL 34/67] ppc/pseries: Add Power11 cpu type, (continued)
- [PULL 34/67] ppc/pseries: Add Power11 cpu type, Nicholas Piggin, 2024/11/03
- [PULL 35/67] target/ppc: use locally stored msr and avoid indirect access, Nicholas Piggin, 2024/11/03
- [PULL 36/67] target/ppc: optimize hreg_compute_pmu_hflags_value, Nicholas Piggin, 2024/11/03
- [PULL 37/67] target/ppc: optimize hreg_compute_pmu_hflags_value, Nicholas Piggin, 2024/11/03
- [PULL 38/67] target/ppc: optimize p9 exception handling routines, Nicholas Piggin, 2024/11/03
- [PULL 39/67] target/ppc: optimize p8 exception handling routines, Nicholas Piggin, 2024/11/03
- [PULL 40/67] target/ppc: optimize p7 exception handling routines, Nicholas Piggin, 2024/11/03
- [PULL 42/67] target/ppc: combine multiple ail checks into one, Nicholas Piggin, 2024/11/03
- [PULL 43/67] target/ppc: reduce duplicate code between init_proc_POWER{9, 10}, Nicholas Piggin, 2024/11/03
- [PULL 46/67] hw/ppc: Implement -dtb support for PowerNV, Nicholas Piggin, 2024/11/03
- [PULL 45/67] spapr: nested: Add Power11 capability support for Nested PAPR guests in TCG L0,
Nicholas Piggin <=
- [PULL 41/67] target/ppc: simplify var usage in ppc_next_unmasked_interrupt, Nicholas Piggin, 2024/11/03
- [PULL 48/67] pnv/xive: TIMA patch sets pre-req alignment and formatting changes, Nicholas Piggin, 2024/11/03
- [PULL 47/67] ppc/xive: Fix ESB length overflow on 32-bit hosts, Nicholas Piggin, 2024/11/03
- [PULL 49/67] pnv/xive2: Define OGEN field in the TIMA, Nicholas Piggin, 2024/11/03
- [PULL 51/67] pnv/xive2: Support for "OS LGS Push" TIMA operation, Nicholas Piggin, 2024/11/03
- [PULL 50/67] ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line", Nicholas Piggin, 2024/11/03
- [PULL 52/67] ppc/xive2: Dump more NVP state with 'info pic', Nicholas Piggin, 2024/11/03
- [PULL 57/67] ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line", Nicholas Piggin, 2024/11/03
- [PULL 44/67] spapr: nested: Add support for DPDES SPR in GSB for TCG L0, Nicholas Piggin, 2024/11/03
- [PULL 54/67] ppc/xive2: Allow 1-byte write of Target field in TIMA, Nicholas Piggin, 2024/11/03