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[Qemu-riscv] [PATCH v2 10/23] riscv: tcg-target: Add the relocation func
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v2 10/23] riscv: tcg-target: Add the relocation functions |
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Date: |
Wed, 19 Dec 2018 19:18:06 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 88 ++++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index d198cfd5f7..a26744052f 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -422,3 +422,91 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
p[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
}
}
+
+/*
+ * Relocations
+ */
+
+static bool reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+ intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
+
+ if (offset == sextreg(offset, 1, 12) << 1) {
+ code_ptr[0] |= encode_sbimm12(offset);
+ return true;
+ }
+
+ return false;
+}
+
+static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+ intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
+
+ if (offset == sextreg(offset, 1, 20) << 1) {
+ code_ptr[0] |= encode_ujimm20(offset);
+ return true;
+ }
+
+ return false;
+}
+
+static bool reloc_call(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+ intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
+ int32_t lo = sextreg(offset, 0, 12);
+ int32_t hi = offset - lo;
+
+ if (offset == hi + lo) {
+ code_ptr[0] |= encode_uimm20(hi);
+ code_ptr[1] |= encode_imm12(lo);
+ return true;
+ }
+
+ return false;
+}
+
+static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
+ intptr_t value, intptr_t addend)
+{
+ uint32_t insn = *code_ptr;
+ intptr_t diff;
+ bool short_jmp;
+
+ tcg_debug_assert(addend == 0);
+
+ switch (type) {
+ case R_RISCV_BRANCH:
+ diff = value - (uintptr_t)code_ptr;
+ short_jmp = diff == sextreg(diff, 0, 12);
+ if (short_jmp) {
+ return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value);
+ } else {
+ /* Invert the condition */
+ insn = insn ^ (1 << 12);
+ /* Clear the offset */
+ insn &= 0x01fff07f;
+ /* Set the offset to the PC + 8 */
+ insn |= encode_sbimm12(8);
+
+ /* Move forward */
+ code_ptr[0] = insn;
+
+ /* Overwrite the NOP with jal x0,value */
+ diff = value - (uintptr_t)(code_ptr + 1);
+ insn = encode_uj(OPC_JAL, TCG_REG_ZERO, diff);
+ code_ptr[1] = insn;
+
+ return true;
+ }
+ break;
+ case R_RISCV_JAL:
+ return reloc_jimm20(code_ptr, (tcg_insn_unit *)value);
+ break;
+ case R_RISCV_CALL:
+ return reloc_call(code_ptr, (tcg_insn_unit *)value);
+ break;
+ default:
+ tcg_abort();
+ }
+}
--
2.19.1
- [Qemu-riscv] [PATCH v2 00/23] Add RISC-V TCG backend support, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 02/23] linux-user: Add host dependency for RISC-V 32-bit, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 03/23] linux-user: Add host dependency for RISC-V 64-bit, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 01/23] elf.h: Add the RISCV ELF magic numbers, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 04/23] exec: Add RISC-V GCC poison macro, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 06/23] riscv: Add the tcg target registers, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 05/23] riscv: Add the tcg-target header file, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 07/23] riscv: tcg-target: Add support for the constraints, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 08/23] riscv: tcg-target: Add the immediate encoders, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 09/23] riscv: tcg-target: Add the instruction emitters, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 10/23] riscv: tcg-target: Add the relocation functions,
Alistair Francis <=
- [Qemu-riscv] [PATCH v2 12/23] riscv: tcg-target: Add the extract instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 11/23] riscv: tcg-target: Add the mov and movi instruction, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 13/23] riscv: tcg-target: Add the out load and store instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 14/23] riscv: tcg-target: Add the add2 and sub2 instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 15/23] riscv: tcg-target: Add branch and jump instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 16/23] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 17/23] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 18/23] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 19/23] riscv: tcg-target: Add the prologue generation and register the JIT, Alistair Francis, 2018/12/19