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Re: [Qemu-riscv] [PATCH v2 18/23] riscv: tcg-target: Add the out op deco
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-riscv] [PATCH v2 18/23] riscv: tcg-target: Add the out op decoder |
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Date: |
Wed, 19 Dec 2018 21:59:27 -0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.3.1 |
On 12/19/18 11:19 AM, Alistair Francis wrote:
> + case INDEX_op_ext32s_i64:
> + case INDEX_op_extrl_i64_i32:
> + case INDEX_op_extrh_i64_i32:
> + case INDEX_op_ext_i32_i64:
> + tcg_out_ext32s(s, a0, a1);
> + break;
This is the last bug that's easy to identify. It shows up quickly in a
linux-user smoke test [1]. Obviously extrl (extract low) and extrh (extract
high) should not be implemented identically.
Fixed thus.
With this, most of the tests pass, when run in a qemu-riscv chroot. The ones
that don't primarily never get started. E.g. the alpha test fails to map
ld.so, for reasons that I have not examined, since it's not a tcg problem.
r~
[1] https://archive.li/o/1YduE/wiki.qemu.org/download/linux-user-test-0.3.tar.gz
---
tcg/riscv/tcg-target.inc.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index f718542d63..6cf8de32b5 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -1614,11 +1614,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ext32s_i64:
case INDEX_op_extrl_i64_i32:
- case INDEX_op_extrh_i64_i32:
case INDEX_op_ext_i32_i64:
tcg_out_ext32s(s, a0, a1);
break;
+ case INDEX_op_extrh_i64_i32:
+ tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32);
+ break;
+
case INDEX_op_mulsh_i32:
case INDEX_op_mulsh_i64:
tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2);
---
- [Qemu-riscv] [PATCH v2 09/23] riscv: tcg-target: Add the instruction emitters, (continued)
- [Qemu-riscv] [PATCH v2 09/23] riscv: tcg-target: Add the instruction emitters, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 10/23] riscv: tcg-target: Add the relocation functions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 12/23] riscv: tcg-target: Add the extract instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 11/23] riscv: tcg-target: Add the mov and movi instruction, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 13/23] riscv: tcg-target: Add the out load and store instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 14/23] riscv: tcg-target: Add the add2 and sub2 instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 15/23] riscv: tcg-target: Add branch and jump instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 16/23] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 17/23] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 18/23] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/12/19
- Re: [Qemu-riscv] [PATCH v2 18/23] riscv: tcg-target: Add the out op decoder,
Richard Henderson <=
- [Qemu-riscv] [PATCH v2 19/23] riscv: tcg-target: Add the prologue generation and register the JIT, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 20/23] riscv: tcg-target: Add the target init code, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 21/23] tcg: Add RISC-V cpu signal handler, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 23/23] configure: Add support for building RISC-V host, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 22/23] dias: Add RISC-V support, Alistair Francis, 2018/12/19
- Re: [Qemu-riscv] [PATCH v2 00/23] Add RISC-V TCG backend support, Richard Henderson, 2018/12/20