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[Qemu-riscv] [PATCH v2 12/23] riscv: tcg-target: Add the extract instruc
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v2 12/23] riscv: tcg-target: Add the extract instructions |
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Date: |
Wed, 19 Dec 2018 19:18:28 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 01b4443d6d..48399480b2 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -596,3 +596,37 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg rd,
tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
tcg_out_opc_imm(s, OPC_LD, rd, rd, 0);
}
+
+static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff);
+}
+
+static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
+ tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
+}
+
+static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
+ tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
+}
+
+static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
+ tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
+}
+
+static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
+ tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
+}
+
+static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
+}
--
2.19.1
- [Qemu-riscv] [PATCH v2 02/23] linux-user: Add host dependency for RISC-V 32-bit, (continued)
- [Qemu-riscv] [PATCH v2 02/23] linux-user: Add host dependency for RISC-V 32-bit, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 03/23] linux-user: Add host dependency for RISC-V 64-bit, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 01/23] elf.h: Add the RISCV ELF magic numbers, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 04/23] exec: Add RISC-V GCC poison macro, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 06/23] riscv: Add the tcg target registers, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 05/23] riscv: Add the tcg-target header file, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 07/23] riscv: tcg-target: Add support for the constraints, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 08/23] riscv: tcg-target: Add the immediate encoders, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 09/23] riscv: tcg-target: Add the instruction emitters, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 10/23] riscv: tcg-target: Add the relocation functions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 12/23] riscv: tcg-target: Add the extract instructions,
Alistair Francis <=
- [Qemu-riscv] [PATCH v2 11/23] riscv: tcg-target: Add the mov and movi instruction, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 13/23] riscv: tcg-target: Add the out load and store instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 14/23] riscv: tcg-target: Add the add2 and sub2 instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 15/23] riscv: tcg-target: Add branch and jump instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 16/23] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 17/23] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 18/23] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 19/23] riscv: tcg-target: Add the prologue generation and register the JIT, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 20/23] riscv: tcg-target: Add the target init code, Alistair Francis, 2018/12/19