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[Qemu-riscv] [PATCH v2 11/23] riscv: tcg-target: Add the mov and movi in
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v2 11/23] riscv: tcg-target: Add the mov and movi instruction |
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Date: |
Wed, 19 Dec 2018 19:18:17 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 86 ++++++++++++++++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index a26744052f..01b4443d6d 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -510,3 +510,89 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
tcg_abort();
}
}
+
+/*
+ * TCG intrinsics
+ */
+
+static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+{
+ if (ret == arg) {
+ return;
+ }
+ switch (type) {
+ case TCG_TYPE_I32:
+ case TCG_TYPE_I64:
+ tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
+ tcg_target_long val)
+{
+ tcg_target_long lo, hi, tmp;
+ int shift, ret;
+
+ if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
+ val = (int32_t)val;
+ }
+
+ lo = sextreg(val, 0, 12);
+ if (val == lo) {
+ tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, lo);
+ return;
+ }
+
+ hi = val - lo;
+ if (TCG_TARGET_REG_BITS == 32 || val == (int32_t)val) {
+ tcg_out_opc_upper(s, OPC_LUI, rd, hi);
+ if (lo != 0) {
+ tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo);
+ }
+ return;
+ }
+
+ /* We can only be here if TCG_TARGET_REG_BITS != 32 */
+ tmp = tcg_pcrel_diff(s, (void *)val);
+ if (tmp == (int32_t)tmp) {
+ tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
+ tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0);
+ ret = reloc_call(s->code_ptr - 2, (tcg_insn_unit *)val);
+ tcg_debug_assert(ret == true);
+ return;
+ }
+
+ /* Look for a single 20-bit section. */
+ shift = ctz64(val);
+ tmp = val >> shift;
+ if (tmp == sextreg(tmp, 0, 20)) {
+ tcg_out_opc_upper(s, OPC_LUI, rd, tmp << 12);
+ if (shift > 12) {
+ tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift - 12);
+ } else {
+ tcg_out_opc_imm(s, OPC_SRAI, rd, rd, 12 - shift);
+ }
+ return;
+ }
+
+ /* Look for a few high zero bits, with lots of bits set in the middle. */
+ shift = clz64(val);
+ tmp = val << shift;
+ if (tmp == sextreg(tmp, 12, 20) << 12) {
+ tcg_out_opc_upper(s, OPC_LUI, rd, tmp);
+ tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift);
+ return;
+ } else if (tmp == sextreg(tmp, 0, 12)) {
+ tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, tmp);
+ tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift);
+ return;
+ }
+
+ /* Drop into the constant pool. */
+ new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0);
+ tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
+ tcg_out_opc_imm(s, OPC_LD, rd, rd, 0);
+}
--
2.19.1
- [Qemu-riscv] [PATCH v2 03/23] linux-user: Add host dependency for RISC-V 64-bit, (continued)
- [Qemu-riscv] [PATCH v2 03/23] linux-user: Add host dependency for RISC-V 64-bit, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 01/23] elf.h: Add the RISCV ELF magic numbers, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 04/23] exec: Add RISC-V GCC poison macro, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 06/23] riscv: Add the tcg target registers, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 05/23] riscv: Add the tcg-target header file, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 07/23] riscv: tcg-target: Add support for the constraints, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 08/23] riscv: tcg-target: Add the immediate encoders, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 09/23] riscv: tcg-target: Add the instruction emitters, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 10/23] riscv: tcg-target: Add the relocation functions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 12/23] riscv: tcg-target: Add the extract instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 11/23] riscv: tcg-target: Add the mov and movi instruction,
Alistair Francis <=
- [Qemu-riscv] [PATCH v2 13/23] riscv: tcg-target: Add the out load and store instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 14/23] riscv: tcg-target: Add the add2 and sub2 instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 15/23] riscv: tcg-target: Add branch and jump instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 16/23] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 17/23] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 18/23] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 19/23] riscv: tcg-target: Add the prologue generation and register the JIT, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 20/23] riscv: tcg-target: Add the target init code, Alistair Francis, 2018/12/19
- [Qemu-riscv] [PATCH v2 21/23] tcg: Add RISC-V cpu signal handler, Alistair Francis, 2018/12/19