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[Qemu-riscv] [PULL 04/14] riscv: Enable VGA and PCIE_VGA
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 04/14] riscv: Enable VGA and PCIE_VGA |
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Date: |
Wed, 26 Dec 2018 09:19:55 -0800 |
From: Alistair Francis <address@hidden>
Enable compile support for VGA devices. This allows the user to conenct
a display by adding '-device bochs-display -display sdl' to their
command line argument.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Logan Gunthorpe <address@hidden>
Tested-by: Andrea Bolognani <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
default-configs/riscv32-softmmu.mak | 3 +++
default-configs/riscv64-softmmu.mak | 3 +++
2 files changed, 6 insertions(+)
diff --git a/default-configs/riscv32-softmmu.mak
b/default-configs/riscv32-softmmu.mak
index c5ea36cba597..dbc93982848a 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -8,3 +8,6 @@ CONFIG_VIRTIO_MMIO=y
CONFIG_CADENCE=y
CONFIG_PCI_GENERIC=y
+
+CONFIG_VGA=y
+CONFIG_VGA_PCI=y
diff --git a/default-configs/riscv64-softmmu.mak
b/default-configs/riscv64-softmmu.mak
index c5ea36cba597..dbc93982848a 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -8,3 +8,6 @@ CONFIG_VIRTIO_MMIO=y
CONFIG_CADENCE=y
CONFIG_PCI_GENERIC=y
+
+CONFIG_VGA=y
+CONFIG_VGA_PCI=y
--
2.18.1
- [Qemu-riscv] [PULL] RISC-V Changes for 3.2, Part 1, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 01/14] hw/riscv/virt: Increase the number of interrupts, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 08/14] RISC-V: Fix CLINT timecmp low 32-bit writes, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 02/14] hw/riscv/virt: Adjust memory layout spacing, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 03/14] hw/riscv/virt: Connect the gpex PCIe, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 04/14] riscv: Enable VGA and PCIE_VGA,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 10/14] RISC-V: Enable second UART on sifive_e and sifive_u, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 05/14] sifive_u: Add clock DT node for GEM ethernet, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 13/14] riscv/cpu: use device_class_set_parent_realize, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 07/14] RISC-V: Add hartid and \n to interrupt logging, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 11/14] sifive_uart: Implement interrupt pending register, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 09/14] RISC-V: Fix PLIC pending bitfield reads, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 12/14] target/riscv/pmp.c: Fix pmp_decode_napot(), Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 14/14] MAINTAINERS: Mark RISC-V as Supported, Palmer Dabbelt, 2018/12/26