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[Qemu-riscv] [PULL 07/14] RISC-V: Add hartid and \n to interrupt logging
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 07/14] RISC-V: Add hartid and \n to interrupt logging |
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Date: |
Wed, 26 Dec 2018 09:19:58 -0800 |
From: Michael Clark <address@hidden>
Add carriage return that was erroneously removed
when converting to qemu_log. Change hard coded
core number to the actual hartid.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_helper.c | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 86f9f4730c88..0234c2d52886 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -445,11 +445,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (RISCV_DEBUG_INTERRUPT) {
int log_cause = cs->exception_index & RISCV_EXCP_INT_MASK;
if (cs->exception_index & RISCV_EXCP_INT_FLAG) {
- qemu_log_mask(LOG_TRACE, "core 0: trap %s, epc 0x" TARGET_FMT_lx,
- riscv_intr_names[log_cause], env->pc);
+ qemu_log_mask(LOG_TRACE, "core "
+ TARGET_FMT_ld ": trap %s, epc 0x" TARGET_FMT_lx "\n",
+ env->mhartid, riscv_intr_names[log_cause], env->pc);
} else {
- qemu_log_mask(LOG_TRACE, "core 0: intr %s, epc 0x" TARGET_FMT_lx,
- riscv_excp_names[log_cause], env->pc);
+ qemu_log_mask(LOG_TRACE, "core "
+ TARGET_FMT_ld ": intr %s, epc 0x" TARGET_FMT_lx "\n",
+ env->mhartid, riscv_excp_names[log_cause], env->pc);
}
}
@@ -511,8 +513,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (hasbadaddr) {
if (RISCV_DEBUG_INTERRUPT) {
- qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld
- ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr);
+ qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": badaddr 0x"
+ TARGET_FMT_lx "\n", env->mhartid, env->badaddr);
}
env->sbadaddr = env->badaddr;
} else {
@@ -536,8 +538,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (hasbadaddr) {
if (RISCV_DEBUG_INTERRUPT) {
- qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld
- ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr);
+ qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": badaddr 0x"
+ TARGET_FMT_lx "\n", env->mhartid, env->badaddr);
}
env->mbadaddr = env->badaddr;
} else {
--
2.18.1
- [Qemu-riscv] [PULL] RISC-V Changes for 3.2, Part 1, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 01/14] hw/riscv/virt: Increase the number of interrupts, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 08/14] RISC-V: Fix CLINT timecmp low 32-bit writes, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 02/14] hw/riscv/virt: Adjust memory layout spacing, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 03/14] hw/riscv/virt: Connect the gpex PCIe, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 04/14] riscv: Enable VGA and PCIE_VGA, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 10/14] RISC-V: Enable second UART on sifive_e and sifive_u, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 05/14] sifive_u: Add clock DT node for GEM ethernet, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 13/14] riscv/cpu: use device_class_set_parent_realize, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 07/14] RISC-V: Add hartid and \n to interrupt logging,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 11/14] sifive_uart: Implement interrupt pending register, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 09/14] RISC-V: Fix PLIC pending bitfield reads, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 12/14] target/riscv/pmp.c: Fix pmp_decode_napot(), Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 14/14] MAINTAINERS: Mark RISC-V as Supported, Palmer Dabbelt, 2018/12/26