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[Qemu-riscv] [PULL 06/14] sifive_u: Set 'clock-frequency' DT property fo
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PULL 06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART |
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Date: |
Wed, 26 Dec 2018 09:19:57 -0800 |
From: Anup Patel <address@hidden>
The 'clock-frequency' DT property is required by U-Boot to compute
the divider value. This patch sets the 'clock-frequency' DT property
of the SiFive UART device tree node (similar to virt machine).
Signed-off-by: Anup Patel <address@hidden>
Signed-off-by: Anup Patel <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 5c41ee5017e4..849fa2e6311a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -241,6 +241,8 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[SIFIVE_U_UART0].base,
0x0, memmap[SIFIVE_U_UART0].size);
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ SIFIVE_U_CLOCK_FREQ / 2);
qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);
--
2.18.1
- [Qemu-riscv] [PULL] RISC-V Changes for 3.2, Part 1, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 01/14] hw/riscv/virt: Increase the number of interrupts, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 08/14] RISC-V: Fix CLINT timecmp low 32-bit writes, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 02/14] hw/riscv/virt: Adjust memory layout spacing, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 03/14] hw/riscv/virt: Connect the gpex PCIe, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 04/14] riscv: Enable VGA and PCIE_VGA, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 10/14] RISC-V: Enable second UART on sifive_e and sifive_u, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 05/14] sifive_u: Add clock DT node for GEM ethernet, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 13/14] riscv/cpu: use device_class_set_parent_realize, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 07/14] RISC-V: Add hartid and \n to interrupt logging, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 11/14] sifive_uart: Implement interrupt pending register, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 09/14] RISC-V: Fix PLIC pending bitfield reads, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 12/14] target/riscv/pmp.c: Fix pmp_decode_napot(), Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 14/14] MAINTAINERS: Mark RISC-V as Supported, Palmer Dabbelt, 2018/12/26