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[Qemu-riscv] [PULL 05/14] sifive_u: Add clock DT node for GEM ethernet
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 05/14] sifive_u: Add clock DT node for GEM ethernet |
Date: |
Wed, 26 Dec 2018 09:19:56 -0800 |
From: Anup Patel <address@hidden>
The GEM ethernet on SiFive unleashed has fixed input clock
of 125MHz as-per SiFive FU540 manual. This patch updates FDT
generation for QEMU sifive_u machine to provide fixed-rate
clock for GEM ethernet.
Signed-off-by: Anup Patel <address@hidden>
Signed-off-by: Anup Patel <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 18 +++++++++++++++++-
include/hw/riscv/sifive_u.h | 3 ++-
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ef07df244241..5c41ee5017e4 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -85,7 +85,8 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
int cpu;
uint32_t *cells;
char *nodename;
- uint32_t plic_phandle;
+ char ethclk_names[] = "pclk\0hclk\0tx_clk";
+ uint32_t plic_phandle, ethclk_phandle;
fdt = s->fdt = create_device_tree(&s->fdt_size);
if (!fdt) {
@@ -197,6 +198,17 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
g_free(cells);
g_free(nodename);
+ nodename = g_strdup_printf("/soc/ethclk");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+ qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ SIFIVE_U_GEM_CLOCK_FREQ);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", 3);
+ qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", 3);
+ ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
+ g_free(nodename);
+
nodename = g_strdup_printf("/soc/address@hidden",
(long)memmap[SIFIVE_U_GEM].base);
qemu_fdt_add_subnode(fdt, nodename);
@@ -208,6 +220,10 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
+ qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+ ethclk_phandle, ethclk_phandle, ethclk_phandle);
+ qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names,
+ sizeof(ethclk_names));
qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1);
qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0);
g_free(nodename);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index e8b4d9ffa3fb..be13cc1304cc 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -63,7 +63,8 @@ enum {
};
enum {
- SIFIVE_U_CLOCK_FREQ = 1000000000
+ SIFIVE_U_CLOCK_FREQ = 1000000000,
+ SIFIVE_U_GEM_CLOCK_FREQ = 125000000
};
#define SIFIVE_U_PLIC_HART_CONFIG "MS"
--
2.18.1
- [Qemu-riscv] [PULL] RISC-V Changes for 3.2, Part 1, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 01/14] hw/riscv/virt: Increase the number of interrupts, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 08/14] RISC-V: Fix CLINT timecmp low 32-bit writes, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 02/14] hw/riscv/virt: Adjust memory layout spacing, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 03/14] hw/riscv/virt: Connect the gpex PCIe, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 04/14] riscv: Enable VGA and PCIE_VGA, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 10/14] RISC-V: Enable second UART on sifive_e and sifive_u, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 05/14] sifive_u: Add clock DT node for GEM ethernet,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 13/14] riscv/cpu: use device_class_set_parent_realize, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 07/14] RISC-V: Add hartid and \n to interrupt logging, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 11/14] sifive_uart: Implement interrupt pending register, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 09/14] RISC-V: Fix PLIC pending bitfield reads, Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 12/14] target/riscv/pmp.c: Fix pmp_decode_napot(), Palmer Dabbelt, 2018/12/26
- [Qemu-riscv] [PULL 14/14] MAINTAINERS: Mark RISC-V as Supported, Palmer Dabbelt, 2018/12/26