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[PATCH v2 16/16] hw/intc: sifive_plic: Fix the pending register range ch
From: |
Bin Meng |
Subject: |
[PATCH v2 16/16] hw/intc: sifive_plic: Fix the pending register range check |
Date: |
Wed, 7 Dec 2022 18:03:35 +0800 |
The pending register upper limit is currently set to
plic->num_sources >> 3, which is wrong, e.g.: considering
plic->num_sources is 7, the upper limit becomes 0 which fails
the range check if reading the pending register at pending_base.
Fixes: 1e24429e40df ("SiFive RISC-V PLIC Block")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
hw/intc/sifive_plic.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 1a792cc3f5..5522ede2cf 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -143,7 +143,8 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr,
unsigned size)
uint32_t irq = (addr - plic->priority_base) >> 2;
return plic->source_priority[irq];
- } else if (addr_between(addr, plic->pending_base, plic->num_sources >> 3))
{
+ } else if (addr_between(addr, plic->pending_base,
+ (plic->num_sources + 31) >> 3)) {
uint32_t word = (addr - plic->pending_base) >> 2;
return plic->pending[word];
@@ -202,7 +203,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr,
uint64_t value,
sifive_plic_update(plic);
}
} else if (addr_between(addr, plic->pending_base,
- plic->num_sources >> 3)) {
+ (plic->num_sources + 31) >> 3)) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid pending write: 0x%" HWADDR_PRIx "",
__func__, addr);
--
2.34.1
- Re: [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize(), (continued)
- [PATCH v2 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser, Bin Meng, 2022/12/07
- [PATCH v2 11/16] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/07
- [PATCH v2 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb, Bin Meng, 2022/12/07
- [PATCH v2 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/07
- [PATCH v2 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev", Bin Meng, 2022/12/07
- [PATCH v2 09/16] hw/intc: sifive_plic: Update "num-sources" property default value, Bin Meng, 2022/12/07
- [PATCH v2 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0, Bin Meng, 2022/12/07
- [PATCH v2 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization, Bin Meng, 2022/12/07
- [PATCH v2 16/16] hw/intc: sifive_plic: Fix the pending register range check,
Bin Meng <=
- Re: [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Philippe Mathieu-Daudé, 2022/12/08
- Re: [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Wilfred Mallawa, 2022/12/08