[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt
From: |
Bin Meng |
Subject: |
[PATCH v2 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC |
Date: |
Wed, 7 Dec 2022 18:03:29 +0800 |
Per chapter 6.5.2 in [1], the number of interupt sources including
interrupt source 0 should be 187.
[1] PolarFire SoC MSS TRM:
https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf
Fixes: 56f6e31e7b7e ("hw/riscv: Initial support for Microchip PolarFire SoC
Icicle Kit board")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
(no changes since v1)
include/hw/riscv/microchip_pfsoc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/microchip_pfsoc.h
b/include/hw/riscv/microchip_pfsoc.h
index 69a686b54a..577efad0c4 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -153,7 +153,7 @@ enum {
#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
-#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
+#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187
#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
--
2.34.1
- Re: [PATCH v2 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order, (continued)
- [PATCH v2 05/16] hw/riscv: spike: Remove misleading comments, Bin Meng, 2022/12/07
- [PATCH v2 06/16] hw/intc: sifive_plic: Drop PLICMode_H, Bin Meng, 2022/12/07
- [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize(), Bin Meng, 2022/12/07
- [PATCH v2 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser, Bin Meng, 2022/12/07
- [PATCH v2 11/16] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/07
- [PATCH v2 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb, Bin Meng, 2022/12/07
- [PATCH v2 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC,
Bin Meng <=
- [PATCH v2 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev", Bin Meng, 2022/12/07
- [PATCH v2 09/16] hw/intc: sifive_plic: Update "num-sources" property default value, Bin Meng, 2022/12/07
- [PATCH v2 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0, Bin Meng, 2022/12/07
- [PATCH v2 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization, Bin Meng, 2022/12/07
- [PATCH v2 16/16] hw/intc: sifive_plic: Fix the pending register range check, Bin Meng, 2022/12/07
- Re: [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Philippe Mathieu-Daudé, 2022/12/08
- Re: [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Wilfred Mallawa, 2022/12/08