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[PATCH v2 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-b
From: |
Bin Meng |
Subject: |
[PATCH v2 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization |
Date: |
Wed, 7 Dec 2022 18:03:34 +0800 |
"hartid-base" and "priority-base" are zero by default. There is no
need to initialize them to zero again.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
---
(no changes since v1)
hw/riscv/opentitan.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 78f895d773..85ffdac5be 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -173,10 +173,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc,
Error **errp)
/* PLIC */
qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
- qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0);
qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
- qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
--
2.34.1
- Re: [PATCH v2 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize(), (continued)
- [PATCH v2 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser, Bin Meng, 2022/12/07
- [PATCH v2 11/16] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/07
- [PATCH v2 13/16] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb, Bin Meng, 2022/12/07
- [PATCH v2 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/07
- [PATCH v2 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev", Bin Meng, 2022/12/07
- [PATCH v2 09/16] hw/intc: sifive_plic: Update "num-sources" property default value, Bin Meng, 2022/12/07
- [PATCH v2 14/16] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0, Bin Meng, 2022/12/07
- [PATCH v2 15/16] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization,
Bin Meng <=
- [PATCH v2 16/16] hw/intc: sifive_plic: Fix the pending register range check, Bin Meng, 2022/12/07
- Re: [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Philippe Mathieu-Daudé, 2022/12/08
- Re: [PATCH v2 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Wilfred Mallawa, 2022/12/08