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[PATCH v3 2/6] target/riscv: Define macros and variables for ss1p13
From: |
Fea.Wang |
Subject: |
[PATCH v3 2/6] target/riscv: Define macros and variables for ss1p13 |
Date: |
Tue, 4 Jun 2024 14:27:43 +0800 |
Add macros and variables for RISC-V privilege 1.13 support.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liwei1518@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.h | 4 +++-
target/riscv/cpu_cfg.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 94600b91fa..4d73486ea2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -96,12 +96,14 @@ extern RISCVCPUProfile *riscv_profiles[];
#define PRIV_VER_1_10_0_STR "v1.10.0"
#define PRIV_VER_1_11_0_STR "v1.11.0"
#define PRIV_VER_1_12_0_STR "v1.12.0"
+#define PRIV_VER_1_13_0_STR "v1.13.0"
enum {
PRIV_VERSION_1_10_0 = 0,
PRIV_VERSION_1_11_0,
PRIV_VERSION_1_12_0,
+ PRIV_VERSION_1_13_0,
- PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0,
+ PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0,
};
#define VEXT_VERSION_1_00_0 0x00010000
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index e1e4f32698..fb7eebde52 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -136,6 +136,7 @@ struct RISCVCPUConfig {
* TCG always implement/can't be user disabled,
* based on spec version.
*/
+ bool has_priv_1_13;
bool has_priv_1_12;
bool has_priv_1_11;
--
2.34.1
- [PATCH v3 0/6] target/riscv: Support RISC-V privilege 1.13 spec, Fea.Wang, 2024/06/04
- [PATCH v3 1/6] target/riscv: Reuse the conversion function of priv_spec, Fea.Wang, 2024/06/04
- [PATCH v3 2/6] target/riscv: Define macros and variables for ss1p13,
Fea.Wang <=
- [PATCH v3 3/6] target/riscv: Support the version for ss1p13, Fea.Wang, 2024/06/04
- [PATCH v3 4/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0, Fea.Wang, 2024/06/04
- [PATCH v3 5/6] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32, Fea.Wang, 2024/06/04
- [PATCH v3 6/6] target/riscv: Reserve exception codes for sw-check and hw-err, Fea.Wang, 2024/06/04