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[PATCH v3 3/6] target/riscv: Support the version for ss1p13
From: |
Fea.Wang |
Subject: |
[PATCH v3 3/6] target/riscv: Support the version for ss1p13 |
Date: |
Tue, 4 Jun 2024 14:27:44 +0800 |
Add RISC-V privilege 1.13 support.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liwei1518@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/cpu.c | 6 +++++-
target/riscv/tcg/tcg-cpu.c | 4 ++++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e9e69b9863..02c1e12a03 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1775,7 +1775,9 @@ static int priv_spec_from_str(const char *priv_spec_str)
{
int priv_version = -1;
- if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) {
+ if (!g_strcmp0(priv_spec_str, PRIV_VER_1_13_0_STR)) {
+ priv_version = PRIV_VERSION_1_13_0;
+ } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) {
priv_version = PRIV_VERSION_1_12_0;
} else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) {
priv_version = PRIV_VERSION_1_11_0;
@@ -1795,6 +1797,8 @@ const char *priv_spec_to_str(int priv_version)
return PRIV_VER_1_11_0_STR;
case PRIV_VERSION_1_12_0:
return PRIV_VER_1_12_0_STR;
+ case PRIV_VERSION_1_13_0:
+ return PRIV_VER_1_13_0_STR;
default:
return NULL;
}
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 60fe0fd060..595d3b5b8f 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -318,6 +318,10 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
cpu->cfg.has_priv_1_12 = true;
}
+ if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
+ cpu->cfg.has_priv_1_13 = true;
+ }
+
/* zic64b is 1.12 or later */
cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
cpu->cfg.cbop_blocksize == 64 &&
--
2.34.1
- [PATCH v3 0/6] target/riscv: Support RISC-V privilege 1.13 spec, Fea.Wang, 2024/06/04
- [PATCH v3 1/6] target/riscv: Reuse the conversion function of priv_spec, Fea.Wang, 2024/06/04
- [PATCH v3 2/6] target/riscv: Define macros and variables for ss1p13, Fea.Wang, 2024/06/04
- [PATCH v3 3/6] target/riscv: Support the version for ss1p13,
Fea.Wang <=
- [PATCH v3 4/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0, Fea.Wang, 2024/06/04
- [PATCH v3 5/6] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32, Fea.Wang, 2024/06/04
- [PATCH v3 6/6] target/riscv: Reserve exception codes for sw-check and hw-err, Fea.Wang, 2024/06/04