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Re: [PATCH v3 4/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0
From: |
Alistair Francis |
Subject: |
Re: [PATCH v3 4/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0 |
Date: |
Thu, 6 Jun 2024 09:58:47 +1000 |
On Tue, Jun 4, 2024 at 4:24 PM Fea.Wang <fea.wang@sifive.com> wrote:
>
> Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in
> mstateen0 that controls access to the hedeleg.
>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Weiwei Li <liwei1518@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_bits.h | 1 +
> target/riscv/csr.c | 8 ++++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 74318a925c..28bd3fb0b4 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -315,6 +315,7 @@
> #define SMSTATEEN0_CS (1ULL << 0)
> #define SMSTATEEN0_FCSR (1ULL << 1)
> #define SMSTATEEN0_JVT (1ULL << 2)
> +#define SMSTATEEN0_P1P13 (1ULL << 56)
> #define SMSTATEEN0_HSCONTXT (1ULL << 57)
> #define SMSTATEEN0_IMSIC (1ULL << 58)
> #define SMSTATEEN0_AIA (1ULL << 59)
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 58ef7079dc..3dcfb343fe 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -2245,6 +2245,10 @@ static RISCVException write_mstateen0(CPURISCVState
> *env, int csrno,
> wr_mask |= SMSTATEEN0_FCSR;
> }
>
> + if (env->priv_ver >= PRIV_VERSION_1_13_0) {
> + wr_mask |= SMSTATEEN0_P1P13;
> + }
> +
> return write_mstateen(env, csrno, wr_mask, new_val);
> }
>
> @@ -2280,6 +2284,10 @@ static RISCVException write_mstateen0h(CPURISCVState
> *env, int csrno,
> {
> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>
> + if (env->priv_ver >= PRIV_VERSION_1_13_0) {
> + wr_mask |= SMSTATEEN0_P1P13;
> + }
> +
> return write_mstateenh(env, csrno, wr_mask, new_val);
> }
>
> --
> 2.34.1
>
>
- [PATCH v3 0/6] target/riscv: Support RISC-V privilege 1.13 spec, Fea.Wang, 2024/06/04
- [PATCH v3 1/6] target/riscv: Reuse the conversion function of priv_spec, Fea.Wang, 2024/06/04
- [PATCH v3 2/6] target/riscv: Define macros and variables for ss1p13, Fea.Wang, 2024/06/04
- [PATCH v3 3/6] target/riscv: Support the version for ss1p13, Fea.Wang, 2024/06/04
- [PATCH v3 4/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0, Fea.Wang, 2024/06/04
- Re: [PATCH v3 4/6] target/riscv: Add 'P1P13' bit in SMSTATEEN0,
Alistair Francis <=
- [PATCH v3 5/6] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32, Fea.Wang, 2024/06/04
- [PATCH v3 6/6] target/riscv: Reserve exception codes for sw-check and hw-err, Fea.Wang, 2024/06/04